Abstract: An error correction method and device for a line structured light 3D camera. The method comprises: placing a 3D calibration plate at different positions in the field of view of the 3D camera, and allowing a relative motion to scan the 3D calibration plate to obtain multiple sets of point cloud data at different positions; processing the point cloud data and calculating corner coordinates of the 3D calibration plate corresponding to each set of point cloud data; constructing an error correction model by using an inclination angle, caused by an error, between a straight line along which the relative motion direction lies and a laser plane of the 3D camera as an error model correction parameter; calculating error correction model parameters according to a space vector constraint relationship between corner points; and applying the model to the point cloud data of a measured object to obtain distortion-free point cloud data.

Abstract: The present invention discloses a radiation-hardened-by-design (RHBD) multi-gate device and a fabrication method thereof. The multi-gate device of the present invention includes a substrate; a source region and a drain region, which are on the substrate; a protruding fin structure and a field dielectric layer between the source region and the drain region on the substrate; a gate dielectric and a gate electrode on the fin structure and the dielectric layer; and two isolation layers separated to each other, which are disposed in the drain region between the adjacent two fins, wherein an interlayer is sandwiched between the two isolation layers.

Abstract: The present invention discloses a radiation-hardened-by-design (RHBD) multi-gate device and a fabrication method thereof. The multi-gate device of the present invention includes a substrate; a source region and a drain region, which are on the substrate; a protruding fin structure and a field dielectric layer between the source region and the drain region on the substrate; a gate dielectric and a gate electrode on the fin structure and the dielectric layer; and two isolation layers separated to each other, which are disposed in the drain region between the adjacent two fins, wherein an interlayer is sandwiched between the two isolation layers.

Abstract: A radiation resistant CMOS device and a method for fabricating the same. The CMOS device includes a substrate, a source region, a drain region and a vertical channel on the substrate. A first dielectric protection region is inserted into the vertical channel at the center of the vertical channel to divide the vertical channel into two parts and has a height equal to the length of the vertical channel. The edge of the first dielectric protection region is 20-100 nm from an outer side of the channel, with a central axis of an silicon platform for an active region as the center. A second dielectric protection region is disposed under the source or drain region, with a length equal to the length of the source or drain region and a height of 10-50 nm. The dielectric protection regions effectively block paths for the source and drain regions collecting charges.