Abstract: The present invention relates to a method for measuring the AC impedance of a battery in a composite power supply power system, comprising the following steps: determining the AC disturbance signal amplitude, operating the DC/DC voltage converter to generate the AC disturbance signal, collecting the output signals of the fuel cell and the lithium battery, calculating the output power of the fuel cell and the lithium battery; calculating the demand power of the load, and when the demand power is stable, calculating the impedance of the lithium battery and the fuel cell separately, otherwise, only the impedance of the fuel cell is calculated.

Abstract: An optical transmission control device comprises a first/second light emitting sub-component, a first/second signal transmission line, a laser driving component, and a microcontroller. The first signal transmission line is connected to the first light emitting sub-component and configured to receive analog signal. The second signal transmission line is configured to receive digital signal. The laser driving component is connected to the first light emitting sub-component, the second light emitting sub-component, and the second signal transmission line. The microcontroller is connected to the laser driving component and configured to receive a data signal.

Abstract: A scalar circuit includes serially connected inverters connected to one another via a plurality of connecting lines. A plurality of input lines are provided to the input of a first inverter in the serially connected inverters. A plurality of feedback lines are provided between the input and output of each inverter. A capacitance and a switch is provided in each connecting line, input line and feedback line. The switch connects a terminal of the capacitance to ground while simultaneously disconnecting the ends of that line from one another. The switches are cooperatively actuated so that the effective composite capacitance in the feedback lines and the connecting lines are substantially equal. In addition, the composite capacitance of in the input lines and the connecting lines are substantially equal.

Abstract: A circuit for weighted addition which includes a transistor having a gate and a plurality of resistance elements. Each resistance element has a first and second end. The first end of each resistance element is impressed with a voltage, and the second end of each resistance element is connected to the gate of the transistor. The circuit is small in size and renders precise and various types of weighted addition possible.

Abstract: A filter device with memory test circuit easily executes a memory test inspite of single-bit data processing to 1 bit data. The filter device with a memory test circuit includes a memory test circuit between a memory means and a shift register, sequentially reads digital data and tests digital data at the external Central Processing Unit (CPU) after converting the data from parallel to serial at the shift register.

Abstract: A sample and hold circuit to reduce hold error when analog data is held and transferred. The circuit includes a plurality of capacitors and inverters for guaranteeing level, selectively holds an input voltage at one capacitor by a first switching means, transfers charged voltage to a second capacitance by a second switching means and reduces data transfer time.

Abstract: A method for directly multiplying an analog and a digital data without converting from analog-to-digital or digital-to-analog. An analog input voltage is provided to a plurality of switches. A digital input voltage including bits b.sub.0 to b.sub.7 which are provided as control signals to the switches. The switch output is integrated giving weights by means of a capacitive coupling, and a sign bit is added by a capacitive coupling CP with a double weight of the most significant bit ("MSB") of the digital input.

Abstract: A large scale integrated neural device has a number of processor elements, each with a number of input lines and a single output line. The neural device also has a local bus with a number of conductors. Each conductor receives one of the output lines from each processor. Any input line of any processor element may be connected to any bus conductor through a switch element. Each processor element generates, as an output, an integrated result of weighted input signals. The switch element ON/OFF state may be programmed from external signals.

Abstract: A circuit calculating the minimum value comprising a plural number of pMOS, wherein source of the plural pMOS are connected to a power source with lower voltage than a drain, the drain is grounded through high resistance, in input voltage is connected to each pMOS, and a common output is connected to a drain of each pMOS.

Abstract: A summing circuit for executing summing of analog data with sign. The summing circuit includes two serially connected inverters INV1 and INV2, each having a feed back line, and selectively inputs data D1 to D8 to one of the first or the second stages, corresponding to positive/negative sign signals S1 to S8.

Abstract: A calculating circuit for outputting a maximum value based on a plurality of inputs. The circuit is comprised of a plurality of nMOS transistors connected in a parallel configuration.

Abstract: A weighted summing circuit for minimizing bias voltage influence includes capacitive coupling and a closed loop inverter. The weighted summing circuit inputs the output of a capacitive coupling CP.sub.1 to serially connected first and second inverters INV.sub.1 and INV.sub.2, and includes grounded weighted capacitances C.sub.32 and C.sub.11, capacitance C.sub.21 connecting the first and the second inverters INV.sub.1 and INV.sub.2, and a capacitive coupling CP.sub.1 such that the closed loop gains of the first and second inverters INV.sub.1 and INV.sub.2 are substantially equal. The closed loop gains of the first and second inverters INV.sub.1 and INV.sub.2 are balanced.

Abstract: A scalar circuit includes serially connected inverters connected to one another via a plurality of connecting lines. A plurality of input lines are provided to the input of a first inverter in the serially connected inverters. A plurality of feedback lines are provided between the input and output of each inverter. A capacitance and a switch is provided in each connecting line, input line and feedback line. The switch connects a terminal of the capacitance to ground while simultaneously disconnecting the ends of that line from one another. The switches are cooperatively actuated so that the effective composite capacitance in the feedback lines and the connecting lines are substantially equal. In addition, the composite capacitance of in the input lines and the connecting lines are substantially equal.

Abstract: The D/A converter comprises: a digital counter receiving a reference clock pluses and a reference voltage as a start signal so as to output a stop signal when the digital counter counts the reference clock pulses until a predetermined number; and a number is reached, and an RC circuit having a resister and a capacitor receiving the reference voltage so as to be charged by a predetermined time constant until the stop signal is inputted to the RC circuit, whereby the RC circuit is charged up to a voltage corresponding to a time distance between the start signal and the stop signal.

Abstract: A memory device for recording a time factor of data includes a threshold element, coupling capacitance, an RC-circuit, and a digital counter. A reference voltage is input to the RC-circuit. The output of the RC-circuit and an input voltage are each input to the coupling capacitance. The output of the coupling capacitance is input to the threshold element. When the voltage received by the threshold element reaches a threshold voltage level, the threshold element generates an output voltage. The digital counter receives the threshold element output voltage and the reference voltage. The digital counter is triggered by the reference voltage to begin counting clock pulses generated by a reference clock. The digital counter is then triggered by the threshold element output voltage to stop counting the clock pulses.

Abstract: An interface circuit for reducing the number of data pins in an LSI circuit. The interface circuit, converts a multivalue input signal of a predetermined level into a binary value or converts a binary output signal into a multivalue of signal a predetermined level and is used as an interface for transferring data in LSI applications.

Abstract: A MOSFET wherein cell includes a MOSFET transistor having a gate connected to an input voltage signal for integration, a source grounded through a high resistance, and a drain connected to a power source. An output capacitor is connected to the source of the MOSFET transistor to complete the MOSFET cell.

Abstract: A multiplication circuit of minimized transfer error having a selector for inputting analog data to one of a plurality of sample hold circuits. The data input in the sample hold circuit is introduced to one of a plurality of multiplication circuits by a multiplexer with multi-input and -output. Data is not transferred between adjacent sample hold circuits.

Abstract: A multiplication circuit for multiplying analog values. The multiplication circuit receives a plurality of input voltages and selects one of the input voltages. The multiplication circuit also includes at least one resistor/capacitor (RC) circuit. The RC circuits includes a resistor for receiving a stepwise start signal and a capacitor, which is connected between a ground potential and the resistor. An output terminal is connected between the resistor and the capacitor. The output terminal outputs an output voltage. The multiplication circuit produces a stop signal when a difference between the selected one of the input voltages and the output voltage is greater than a predetermined value. The multiplication circuit selectively increases or decreases a count value by a number of clock pulses that occur between the stepwise start signal and the stop signal, The multiplication circuit produces a count signal, which is indicative of the count value.

Abstract: A subtracting circuit which is capable of performing highly accurate, small scale subtraction. The subtracting circuit includes a first input capacitance receiving a first input voltage, a first set of inverters connected with an output terminal of the first input capacitance, a second input capacitance connected with an output terminal of the first set of inverters and receiving a second input voltage, and a second set of inverters connected with an output terminal of the second input capacitance, each set of inverters having capacitive feedback. The subtracting result is output from the second set of inverters.