Abstract: A puller includes a collar, claws, a synchronizer and an abutting assembly. The collar includes slots and pivotal connectors located corresponding to the slots. The claws are pivotally connected to the pivotal connectors. Each of the claws includes a protuberance movable in a corresponding one of the slots. The synchronizer includes a receiving portion for receiving the protuberances. The synchronizer is movable in the collar between an opening position and a closing position. In the opening position, the synchronizer opens the claws by the protuberances. In the closing position, the synchronizer closes the claws by the protuberances. The synchronizer is extensible from the collar.

Abstract: The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.

Abstract: The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.

Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

Abstract: A claw assembly includes a collar, claws and a synchronizer. The collar includes slots. The claws are pivotally connected to the collar. Each of the claws includes a protuberance extending into the collar via one of the slots. The protuberances are movable along the slots. The synchronizer includes a receiving portion for receiving the protuberances. The receiving portion of the synchronizer is movable in the collar between an opening position and a closing position. The synchronizer opens the claws by the protuberances in the opening position. The synchronizer closes the claws by the protuberances in the closing position.

Abstract: A puller includes a collar, claws, a synchronizer and an abutting element. The collar includes slots and pivotal connectors located corresponding to the slots. The claws are pivotally connected to the pivotal connectors. Each of the claws includes a protuberance movable in and along a corresponding one of the slots. The synchronizer includes a receiving portion for receiving the protuberances. The synchronizer is movable in the collar between an opening position and a closing position. In the opening position, the synchronizer opens the claws by the protuberances. In the closing position, the synchronizer closes the claws by the protuberances. The abutting element is extensible from the collar.

Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

Abstract: A puller includes a collar, claws, a synchronizer and a threaded rod. The collar includes a space, a screw hole in communication with the space, slots in communication with the space, and pivotal connectors located corresponding to the slots. The claws are pivotally connected to the pivotal connectors. Each of the claws includes a protuberance movable in and along a corresponding one of the slots. The synchronizer includes a receiving portion for receiving the protuberances. The synchronizer is movable in the collar between an opening position and a closing position. In the opening position, the synchronizer opens the claws by the protuberances. In the closing position, the synchronizer closes the claws by the protuberances. The threaded rod is inserted in the screw hole of the collar.

Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Abstract: A puller includes a collar, claws, a synchronizer and an abutting assembly. The collar includes slots and pivotal connectors located corresponding to the slots. The claws are pivotally connected to the pivotal connectors. Each of the claws includes a protuberance movable in a corresponding one of the slots. The synchronizer includes a receiving portion for receiving the protuberances. The synchronizer is movable in the collar between an opening position and a closing position. In the opening position, the synchronizer opens the claws by the protuberances. In the closing position, the synchronizer closes the claws by the protuberances. The synchronizer is extensible from the collar.

Abstract: A puller includes a collar, claws, a synchronizer and an abutting element. The collar includes slots and pivotal connectors located corresponding to the slots. The claws are pivotally connected to the pivotal connectors. Each of the claws includes a protuberance movable in and along a corresponding one of the slots. The synchronizer includes a receiving portion for receiving the protuberances. The synchronizer is movable in the collar between an opening position and a closing position. In the opening position, the synchronizer opens the claws by the protuberances. In the closing position, the synchronizer closes the claws by the protuberances. The abutting element is extensible from the collar.

Abstract: A claw assembly includes a collar, claws and a synchronizer The collar includes slots. The claws are pivotally connected to the collar. Each of the claws includes a protuberance extending into the collar via one of the slots. The protuberances are movable along the slots. The synchronizer includes a receiving portion for receiving the protuberances. The receiving portion of the synchronizer is movable in the collar between an opening position and a closing position. The synchronizer opens the claws by the protuberances in the opening position. The synchronizer closes the claws by the protuberances in the closing position.

Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Abstract: A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.

Abstract: A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.