Abstract: This disclosure relates to an X-ray reflectometry apparatus and a method for measuring a three-dimensional nanostructure on a flat substrate. The X-ray reflectometry apparatus comprises an X-ray source, an X-ray reflector, a 2-dimensional X-ray detector, and a two-axis moving device. The X-ray source is for emitting X-ray. The X-ray reflector is configured for reflecting the X-ray onto a sample surface. The 2-dimensional X-ray detector is configured to collect a reflecting X-ray signal from the sample surface. The two-axis moving device is configured to control two-axis directions of the 2-dimensional X-ray detector to move on at least one of x-axis and z-axis with a formula concerning an incident angle of the X-ray with respect to the sample surface for collecting the reflecting X-ray signal.

Abstract: A computing system receives a request to verify a user, the request comprising an indication of a jurisdiction in which the user will be verified. Based on the request, the computing system collects information related to the user. Based on the request, the computing system identifies a workflow corresponding to the jurisdiction. The workflow defines conditions for obtaining a verified status in the jurisdiction. The computing system executes the workflow to verify the user. The computing system hashes the verification record using a zero-knowledge proof protocol. The computing system generates a non-fungible token corresponding to the verification record. The non-fungible token is associated with a hashed version of the verification record. The computing system broadcasts the non-fungible token to a blockchain.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: A delay line includes at least one delay cell, wherein the delay line utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor. In addition, a memory control circuit includes a delay locked loop (DLL) having at least one delay cell. The delay locked loop utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor.

Abstract: A memory access control method is provided. By decoding a read-write command, a mode register set (MRS) signal is generated. When the MRS signal is enabled, a latch outputs a bank-select signal. The bank-select signal is then decoded to generate a register-select signal. Then, an address signal is written into a register selected by the register-select signal. The value of a certain register can be used to determine whether to enable the error check function. Thus, the next generation memory structure with the CRC function can be compatible with the conventional memory structure.

Abstract: A delay line includes at least one delay cell, wherein the delay line utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor. In addition, a memory control circuit includes a delay locked loop (DLL) having at least one delay cell. The delay locked loop utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor.

Abstract: A cyclic redundancy check (CRC) is used for improving error check coverage during memory access. In memory reading process, a part of read data is outputted from the memory via a CRC bus, and a CRC result and the other part of the read data are outputted from the memory via a data bus.

Abstract: A semiconductor includes a first sensor amplifier, a second sensor amplifier, a first switch and a second switch. The first sensor amplifier is coupled between a local data line and a memory unit to amplify signals of the memory unit. The second sensor amplifier is coupled to a middle data line to amplify signals of the middle data line. The first switch is coupled between the middle data line and the local data line to equalize voltage levels between the middle data line and the local data line by turning on the first switch according to a data control signal. The second switch is coupled between the local data line and a reference voltage to equalize the local data line to the voltage level of the reference voltage by turning on the second switch according to a local data control signal.

Abstract: In a delay locked loop, a phase detector compares the phases of an input signal and an output signal; a delay line delays the input signal, wherein the delay line includes a plurality of unit delay elements connected in series and the value of the unit delay of each of the unit delay elements is adjusted by a control signal; a multiplexer selects a number of delay stages of the unit delay elements according to the phase comparison result and generates the output signal. The control signal is related to a clock information signal. When the input signal is high frequency, the value of the unit delay would be small; and when the input signal is low frequency, the value of the unit delay would be large.

Abstract: A memory access control method is provided. By decoding a read-write command, a mode register set (MRS) signal is generated. When the MRS signal is enabled, a latch outputs a bank-select signal. The bank-select signal is then decoded to generate a register-select signal. Then, an address signal is written into a register selected by the register-select signal. The value of a certain register can be used to determine whether to enable the error check function. Thus, the next generation memory structure with the CRC function can be compatible with the conventional memory structure.

Abstract: A semiconductor includes a first sensor amplifier, a second sensor amplifier, a first switch and a second switch. The first sensor amplifier is coupled between a local data line and a memory unit to amplify signals of the memory unit. The second sensor amplifier is coupled to a middle data line to amplify signals of the middle data line. The first switch is coupled between the middle data line and the local data line to equalize voltage levels between the middle data line and the local data line by turning on the first switch according to a data control signal. The second switch is coupled between the local data line and a reference voltage to equalize the local data line to the voltage level of the reference voltage by turning on the second switch according to a local data control signal.

Abstract: A memory comprising a memory array, a sensor amplifier, and a column driver/decoder. The memory comprises a plurality of memory cells. The sensor amplifier is disposed on one side of the memory array for accessing the memory cells of the memory array. The column driver/decoder is disposed on the opposite side of the memory array for selecting the memory cells of the memory array.

Abstract: A memory and an operation method thereof are provided. The present invention divides memory banks of the memory into a plurality of memory groups, wherein each memory group has an independent driving power for providing an operating voltage to the corresponding memory bank in the memory group. The present invention specifies two tRRD times which are an inter-group interval and an intra-group interval. The intra-group interval is the minimum time interval between selecting one row of memory banks in a memory group to selecting another row in the memory banks of the same memory group and the inter-group interval is the minimum time interval between selecting one row of the memory banks in one memory group to selecting another row in a different memory group. Further, the inter-group interval is shorter than or equal to the intra-group interval.

Abstract: Received read commands and address signals are respectively decoded into internal column strobe signals and internal address signals for reading data out of a data storage portion of a memory. A waiting interval during which a readout data becomes ready is simulated or a transmission path on which the readout data is transmitted is simulated. When the simulation result indicates the readout data is ready, an error check operation is performed on the readout data. The operation interval of the error check is simulated. When the simulation for the error check operation indicates that the error check is completed, an error check result is sent out of the memory.

Abstract: A memory and an operation method thereof are provided. The present invention divides memory banks of the memory into a plurality of memory groups, wherein each memory group has an independent driving power for providing an operating voltage to the corresponding memory bank in the memory group. The present invention specifies two tRRD times which are an inter-group interval and an intra-group interval. The intra-group interval is the minimum time interval between selecting one row of memory banks in a memory group to selecting another row in the memory banks of the same memory group and the inter-group interval is the minimum time interval between selecting one row of the memory banks in one memory group to selecting another row in a different memory group. Further, the inter-group interval is shorter than or equal to the intra-group interval.

Abstract: A cyclic redundancy check (CRC) is used for improving error check coverage during memory access. In memory reading process, a part of read data is outputted from the memory via a CRC bus, and a CRC result and the other part of the read data are outputted from the memory via a data bus.

Abstract: In a delay locked loop, a phase detector compares the phases of an input signal and an output signal; a delay line delays the input signal, wherein the delay line includes a plurality of unit delay elements connected in series and the value of the unit delay of each of the unit delay elements is adjusted by a control signal; a multiplexer selects a number of delay stages of the unit delay elements according to the phase comparison result and generates the output signal. The control signal is related to a clock information signal. When the input signal is high frequency, the value of the unit delay would be small; and when the input signal is low frequency, the value of the unit delay would be large.

Abstract: A method for repairing defects in a memory is disclosed. The method includes: performing a defect test on the memory to obtain at least one defect address of the memory, storing the at least one defect address into a storage media, storing the at least one defect address stored in the storage media into a storage module of the memory, determining whether a target address matches any of the at least one defect address after an access request pointing to the target address of the memory is received, and accessing a redundant cell of a memory cell directed by the target address in response to the access request.

Abstract: An input receiver includes a negative voltage generator and an amplifier for amplifying an input signal. The negative voltage generator generates a negative voltage. The amplifier is coupled to the input signal, a supply voltage, and the negative voltage, and amplifies the input signal to generate an amplified signal accordingly.