Patents by Inventor Weiliang Jing

Weiliang Jing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250212416
    Abstract: This disclosure provides a ferroelectric memory, a three-dimensional integrated circuit, and an electronic device, and relates to the field of semiconductor chip technologies, to improve an anti-interference capability of a capacitor. The ferroelectric memory includes a capacitor. The capacitor includes a first stacked layer, a first conductive pillar, a second conductive pillar, a first ferroelectric layer, and a second ferroelectric layer. The first stacked layer includes a first conductive portion and a second conductive portion that are connected. The first conductive pillar penetrates the first conductive portion, and the second conductive pillar penetrates the second conductive portion. The first ferroelectric layer penetrates the first conductive portion and is disposed around the first conductive pillar, and the second ferroelectric layer penetrates the second conductive portion and is disposed around the second conductive pillar.
    Type: Application
    Filed: March 12, 2025
    Publication date: June 26, 2025
    Inventors: Kailiang HUANG, Weiliang JING, Shihui YIN, Zhengbo WANG, Heng LIAO
  • Publication number: 20250203979
    Abstract: Embodiments of this disclosure provide a chip and a preparation method thereof, and an electronic device. This resolves a problem that a gate control capability of the chip decreases as a size of a device shrinks. The chip includes a substrate, a source, a drain, a first channel hole, a channel layer, a gate, and a gate dielectric layer. A side wall surface of the first channel hole is a concave wall surface, and the channel layer is formed on the concave wall surface. The concave wall surface includes a wall surface of a concave cavity formed by a part that is of a side wall of the first channel hole and that is concave in a direction parallel to the substrate. In addition, the concave cavity is located between the source and the drain.
    Type: Application
    Filed: February 25, 2025
    Publication date: June 19, 2025
    Inventors: Kailiang HUANG, Weiliang JING, Wenqiang ZHANG, Zhaogui WANG, Zhengbo WANG, Heng LIAO, Gouri Sankar KAR, Kaustuv BANERJEE
  • Publication number: 20250037749
    Abstract: This disclosure relates to a bit line reading circuit, a memory, and an electronic device. An example bit line reading circuit includes a bit line connected to a ferroelectric memory cell. The bit line reading circuit further includes a reference line, a sense amplifier, and a precharge circuit. The sense amplifier and the precharge circuit are separately connected to the bit line and the reference line. The bit line reading circuit further includes a first switch connected to the bit line between the sense amplifier and the precharge circuit, and a second switch connected to the reference line between the sense amplifier and the precharge circuit.
    Type: Application
    Filed: October 18, 2024
    Publication date: January 30, 2025
    Inventors: Shihui YIN, Weiliang JING, Bingwu JI, Sitong BU, Zhengbo WANG, Heng LIAO
  • Publication number: 20250008746
    Abstract: Embodiments of this disclosure relate to a vertical channel transistor structure. An example vertical channel transistor structure includes a stacked structure. The stacked structure includes a first metal layer, a first contact layer, an insulation dielectric layer, a second contact layer, a second metal layer, and a groove. The first contact layer is located between the first metal layer and the insulation dielectric layer, and the second contact layer is located between the second metal layer and the insulation dielectric layer. The groove penetrates the second metal layer, the second contact layer, the insulation dielectric layer, and the second contact layer. The groove is at least partially recessed into the first metal layer. The groove includes a semiconductor channel layer, a gate oxygen dielectric layer, and a gate.
    Type: Application
    Filed: September 13, 2024
    Publication date: January 2, 2025
    Inventors: Kailiang HUANG, Weiliang JING, Zhaogui WANG, Junxiao FENG, Zhengbo WANG
  • Publication number: 20240259022
    Abstract: A logic gate circuit includes a pull-up network, a pull-down network, a signal output end, at least one signal input end, a first voltage end, and a second voltage end. The pull-up network includes a first gate and a second gate. A first electrode of the first NFET and the first gate are connected to the first voltage end. A second electrode of the first NFET and the second gate are connected to the signal output end. The pull-down network includes a second NFET. The pull-down network is connected to the signal output end, the at least one signal input end, and the second voltage end. The pull-down network is configured to: control the second NFET based on a voltage of the at least one signal input end, and pull down a voltage of the signal output end by using a voltage of the second voltage end.
    Type: Application
    Filed: April 8, 2024
    Publication date: August 1, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ying Wu, Weiliang Jing, Zhaozhao Hou, Renshi Fan, JEFFREY JUNHAO XU
  • Patent number: 12014058
    Abstract: A stacked memory includes a volatile memory die and a non-volatile memory die that are stacked together. The non-volatile memory die includes a non-volatile storage array and a peripheral circuit. The peripheral circuit includes a power integrity circuit and a signal integrity circuit. The power integrity circuit is configured to perform power integrity optimization on a power supply obtained from a lower-layer die and then transmit the power supply to an upper-layer die. The signal integrity circuit is configured to perform signal integrity optimization on a signal obtained from a lower-layer die and then transmit the signal to an upper-layer die.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: June 18, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Weiliang Jing, Zhengbo Wang, Jingjie Cui
  • Publication number: 20240172450
    Abstract: A ferroelectric memory includes a substrate and a plurality of memory cells formed on the substrate. Each memory cell includes a transistor and a plurality of ferroelectric capacitors. In other words, each memory cell includes at least two ferroelectric capacitors to implement multi-bit data storage. The transistor and the plurality of ferroelectric capacitors are arranged in a first direction perpendicular to the substrate. Any ferroelectric capacitor includes a first electrode layer, a second electrode layer, and a ferroelectric layer formed between the first electrode layer and the second electrode layer. The first electrode layers of every two adjacent ferroelectric capacitors of the plurality of ferroelectric capacitors are in contact, to form a shared first electrode layer that extends in the first direction.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 23, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Weiliang Jing, Kailiang Huang, Junxiao Feng, Zhengbo Wang
  • Publication number: 20240121942
    Abstract: A memory comprises a substrate and a plurality of storage units formed on the substrate. Each of the storage units includes a transistor and a capacitor electrically connected to the transistor. The transistor includes a gate, a semiconductor layer, a first electrode, a second electrode, and a gate dielectric layer. The first electrode and the second electrode are arranged in a first direction. The gate is located between the first electrode and the second electrode. The semiconductor layer is located on one of two opposite sides of the gate in a second direction. The semiconductor layer is electrically connected separately to the first electrode and the second electrode, the gate and the semiconductor layer are isolated from each other by the gate dielectric layer, and the second direction is a direction parallel to the substrate.
    Type: Application
    Filed: December 16, 2023
    Publication date: April 11, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Weiliang Jing, Kailiang Huang, Junxiao Feng, Zhengbo Wang
  • Publication number: 20230371229
    Abstract: A thin-film transistor (TFT) includes a gate, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer. The gate includes a gate base located at a top portion and a gate body extending from the gate base to a bottom portion. The first electrode is located at the bottom portion. The second electrode is located between the first electrode and the gate base. The first dielectric layer is disposed between the second electrode and the first electrode, and the first dielectric layer is configured to separate the first electrode from the second electrode. The second dielectric layer covers a surface of the gate base and a surface of the gate body. The semiconductor layer is disposed along a side surface of the gate body, and the second dielectric layer separates the semiconductor layer from the gate.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Weiliang Jing, Kailiang Huang, Junxiao Feng, Zhengbo Wang
  • Publication number: 20230342312
    Abstract: Embodiments of this application disclose a storage device and a computer device, and belong to the field of computer technologies. The storage device includes a first PCM, a main memory, and a controller. The first PCM and the controller are packaged in a same chip. A latency of the first PCM is less than that of the main memory, and storage density of the main memory is greater than that of the first PCM. The controller is configured to store data in the first PCM and the main memory based on a read/write temperature of the data, where the first PCM is a cache of the main memory. According to embodiments of this application, a cache capacity of the storage device can be increased, and device costs can be reduced.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 26, 2023
    Inventors: Xiaoming ZHU, Weiliang JING
  • Publication number: 20230276636
    Abstract: Example ferroelectric memories and storage devices are described One example ferroelectric memory includes at least one bit cell. A bit cell in the at least one bit cell includes a plurality of ferroelectric capacitors and a first transistor. The first transistor includes a first gate, a first channel, a first source, and a first drain. The first source and the first drain are located at two ends of the first channel. One electrode of each of the plurality of ferroelectric capacitors is formed on the first gate.
    Type: Application
    Filed: May 3, 2023
    Publication date: August 31, 2023
    Inventors: Jeffrey Junhao XU, Weiliang JING, Sitong BU, Yichen FANG, Ying WU, Zhaozhao HOU, Wanliang TAN, Heng ZHANG, Yu ZHANG
  • Publication number: 20230139599
    Abstract: A stacked memory includes a volatile memory die and a non-volatile memory die that are stacked together. The non-volatile memory die includes a non-volatile storage array and a peripheral circuit. The peripheral circuit includes a power integrity circuit and a signal integrity circuit. The power integrity circuit is configured to perform power integrity optimization on a power supply obtained from a lower-layer die and then transmit the power supply to an upper-layer die. The signal integrity circuit is configured to perform signal integrity optimization on a signal obtained from a lower-layer die and then transmit the signal to an upper-layer die.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 4, 2023
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Weiliang Jing, Zhengbo Wang, Jingjie Cui