Abstract: A technology flushing a hierarchical cache structure based on a designated key identification code and a designated address. A processor includes a first core and a last level cache (LLC). The first core includes a decoder, a memory ordering buffer, and a first in-core cache module. In response to an Instruction Set Architecture (ISA) instruction that requests to flush a hierarchical cache structure according to a designated key identification code and a designated address, the decoder outputs at least one microinstruction. According to the at least one microinstruction, a flushing request with the designated key identification code and the designated address is provided to the first in-core cache module through the memory ordering buffer, and then the first in-core cache module provides the LLC with the flushing request, so that the LLC flushes its matching cache line which matches the designated key identification code and the designated address.

Abstract: Disclosed in the present invention are a method and a system for ensuring the failure atomicity in a non-volatile memory, which belong to the field of computer storage.

Abstract: Disclosed in the present invention are a method and a system for ensuring the failure atomicity in a non-volatile memory, which belong to the field of computer storage.

Abstract: A method of pre-controlling the shapes of a continuous-casting slab head and tail for reducing the cut amount of the head and tail of the hot rolling intermediate slab. The continuous-casting slab head and tail, is cut into a shape such that an end surface of the head concaves inwards and the tail projects outwards. The head and tail of a slab is cut in a curve that is symmetric to the center line in width thereof. Arc height, i.e. a maximum value of the concave amount at the head or that of the projection amount at the tail, is controlled within 0 mm-50 mm.

Abstract: A method of pre-controlling the shapes of a continuous-casting slab head and tail for reducing the cut amount of the head and tail of the hot rolling intermediate slab. The continuous-casting slab head and tail, is cut into a shape such that an end surface of the head concaves inwards and the tail projects outwards. The head and tail of a slab is cut in a curve that is symmetric to the center line in width thereof. Arc height, i.e. a maximum value of the concave amount at the head or that of the projection amount at the tail is controlled within 0 mm-50 mm.

Abstract: A method and apparatus for a telephone line interface or data access arrangement (DAA) which includes a shunt regulator in series with a line modulator. A sense resistor is placed in series between the shunt regulator and the line modulator to provide a measurement of the amount of current distortion in the DAA. The line modulator contains a Darlington pair which reduces the amount of current drawn by the line modulator, allowing the sense resistor to sense a majority of the system current. The voltage across the sense resistor is fed back to the line modulator. The line modulator is capable of adjusting the AC modulation and the DC termination presented to the telephone line. The method includes drawing power from the telephone line using a shunt regulator, modulating the telephone line in series with the shunt regulator, sensing a level of distortion in the DAA, and feeding the sensed level of distortion to the line modulator.

Abstract: A line powered data access arrangement (DAA) is disclosed which adaptively allows proper operation with power supplied from a telephone line as conditions warrant, while at the same time satisfying the relevant requirements of many countries. In the line powered codec, a startup procedure for the international line powered codec uses register settings, e.g., country-specific register settings, which are powered and maintained from the low voltage side (e.g., from the PC or modem side) of the line powered codec. In this way, even during low line power conditions the programmed state of the line powered codec can be maintained, thus a default condition will not necessarily returned to by the line powered codec upon reset due to a power loss in the telephone line. In another aspect, a charge storage device such as a charge capacitor is charged from a charge pump formed from a differential clock signal from the low voltage side.

Abstract: A method and apparatus for a data access arrangement (DAA) which includes a line modulator containing capacitive elements to increase system stability. The invention provides improved stability during system startup and normal system operation. The line modulator is capable of adjusting the AC modulation and the DC termination presented to the telephone line. Capacitive elements are added to the modulator to provide enhanced system stability. The method includes drawing power from the telephone line, modulating the telephone line, sensing a level of distortion through the line modulator, feeding the sensed level of distortion to the line modulator, and using capacitive circuits to provide additional system stability.

Abstract: A line powered data access arrangement (DAA) is disclosed which adaptively allows proper operation with power supplied from a telephone line as conditions warrant, while at the same time satisfying the relevant requirements of many countries. In the line powered codec, a startup procedure for the international line powered codec uses register settings, e.g., country-specific register settings, which are powered and maintained from the low voltage side (e.g., from the PC or modem side) of the line powered codec. In this way, even during low line power conditions the programmed state of the line powered codec can be maintained, thus a default condition will not necessarily returned to by the line powered codec upon reset due to a power loss in the telephone line. In another aspect, a charge storage device such as a charge capacitor is charged from a charge pump formed from a differential clock signal from the low voltage side.

Abstract: A circuit provides a modulation signal to an input terminal of a line modulator which places a line current modulated in accordance with the modulation signal on a telephone line. An amplifier of the circuit amplifies an analog input signal to provide the modulation signal at an output terminal. A first resistor and a first capacitor are coupled in series between a first input terminal of the amplifier and the line, and a second resistor and a second capacitor are coupled in series between a second input terminal of the amplifier and the line. First and second precharge amplifiers are used to precharge the first and second capacitors, respectively, to reduce DC setup time.

Abstract: A low power differential comparator wherein the input stage bias is used not only to set a bias level but is also used to set the hysteresis level of the differential comparator circuit. The positive and/or negative inputs to the differential comparator circuit are referred to ground to reduce the total DC current draw, e.g., by a factor of 7. The multiple use of the input stage bias and grounded connections to the positive and/or negative inputs reduce the overall current requirements of the differential comparator circuit substantially while maintaining full operating speed as compared to conventional differential comparator circuits. In one embodiment using the low power differential comparator circuit, a clock receiver implements hysteresis which is relatively independent from variations in environmental factors such as temperature, and from power supply variations. In this embodiment, the input stage of a low power comparator circuit is biased by the output of a bias circuit.

Abstract: A circuit and method for reducing a propagation delay associated with a comparator and a comparator employing the circuit or method. In one embodiment, the comparator, includes: (1) an input stage that receives a differential input signal and develops therefrom a threshold signal, (2) an output stage, coupled to the input stage, that develops a level shifted single-ended output signal as a function of the threshold signal, and (3) a speed-up circuit, associated with the input stage, that reduces a time period to develop the determinant signal thereby decreasing a propagation delay in developing the level shifted single-ended output signal from the differential input signal.