Abstract: The present disclosure describes a semiconductor device with substantially uniform gate regions and a method for forming the same. The method includes forming a fin structure on a substrate, the fin structure including one or more nanostructures. The method further includes removing a portion of the fin structure to expose an end of the one or more nanostructures and etching the end of the one or more nanostructures with one or more etching cycles. Each etching cycle includes purging the fin structure with hydrogen fluoride (HF), etching the end of the one or more nanostructures with a gas mixture of fluorine (F2) and HF, and removing an exhaust gas mixture including an etching byproduct. The method further includes forming an inner spacer in the etched end of the one or more nanostructures.

Abstract: The disclosure provides an adaptive self-learning method and an adaptive self-learning system. The adaptive self-learning method includes steps of inputting a first complex model and unlabeled data to an adaptive semi-supervised learning module and performing a pre-semi-supervised learning module to generate an average precision variation. If the average precision variation does not satisfy a condition value at any one time out of an inference count, the semi-supervised learning module is performed. After performing the semi-supervised learning module, the steps include performing a self-learning module for refining the target model, and then the trained target model is disposed to a site device. The site device deploys the trained target model to perform an object detection procedure.

Abstract: A method for fabricating a semiconductor arrangement includes performing a first etching of a semiconductive structure to expose a first portion of a sidewall of a first layer adjacent the semiconductive structure. The first etching forms a first protective layer on the first portion of the sidewall of the first layer, and the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching interacting with the semiconductive structure. The method includes performing a first flash to remove at least some of the first protective layer.

Abstract: A semiconductor structure includes: a substrate; a fin protruding from the substrate, wherein the fin comprises a first semiconductor layer, a dielectric layer and a second semiconductor layer arranged over one another; and a gate electrode. The gate electrode includes: a first conductive portion extending from a sidewall of the first semiconductor layer to an upper surface of the substrate in a conformal manner; and a second conductive portion extending over the second semiconductor layer in a conformal manner.

Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

Abstract: A semiconductor structure includes: a substrate and a fin protruding from the substrate. The fin comprises a first semiconductive layer over the substrate, a second semiconductive layer over the first semiconductive layer, and a dielectric layer disposed between the first semiconductive layer and the second semiconductive layer and electrically isolated from the first semiconductive layer and the second semiconductive layer. The semiconductor structure further includes a gate electrode including: a first conductive portion extending along two opposite sidewalls of the first semiconductive layer and along an upper surface of the substrate; and a second conductive portion electrically isolated from the first conductive portion and extending along two opposite sidewalls of the second semiconductive layer and along an upper surface of the fin.

Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a polysilicon structure around the superlattice structure, forming a source/drain opening within the superlattice structure, forming a first conductivity type S/D region within a first portion of the S/D opening, forming an isolation layer on the first conductivity type S/D region and within a second portion of the S/D opening, forming a second conductivity type S/D region on the isolation layer and within a third portion the S/D opening, and replacing the polysilicon structure and the second nanostructured layers with a gate structure that surrounds the first nanostructured layers. Materials of the first and second nanostructured layers are different from each other and the second conductivity type is different from the first conductivity type.

Abstract: A method for fabricating a semiconductor arrangement includes performing a first etching of a semiconductive structure to expose a first portion of a sidewall of a first layer adjacent the semiconductive structure. The first etching forms a first protective layer on the first portion of the sidewall of the first layer, and the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching interacting with the semiconductive structure. The method includes performing a first flash to remove at least some of the first protective layer.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a polysilicon structure around the superlattice structure, forming a source/drain opening within the superlattice structure, forming a first conductivity type S/D region within a first portion of the S/D opening, forming an isolation layer on the first conductivity type S/D region and within a second portion of the S/D opening, forming a second conductivity type S/D region on the isolation layer and within a third portion the S/D opening, and replacing the polysilicon structure and the second nanostructured layers with a gate structure that surrounds the first nanostructured layers. Materials of the first and second nanostructured layers are different from each other and the second conductivity type is different from the first conductivity type.

Abstract: A horizontal grinder rotor includes a grinding ring, multiple blades, and a center body. The grinding ring, the multiple blades and the central body are formed by 3D printing. The multiple blades are located between the grinding ring and the central body, and the multiple blades are arranged at intervals. The multiple blades are arranged in pairs and symmetrical with respect to the central body, and the horizontal grinder rotor further comprises one or more pins, the one or more pins are provided on at least one side of each of the multiple blades.

Abstract: A method of making a silicon-carbon pre-lithium composite anode material is provided. The method includes: nanoizing silicon materials to obtain nano-silicon particles, adding carbon materials and polymer into the nano-silicon particles for homogenization treatment to obtain a silicon-carbon composite; providing a pre-lithium nanomaterial; mixing the silicon-carbon composite and the pre-lithium nanomaterial to granulate to obtain a silicon-carbon pre-lithium composite precursor; and sintering the silicon-carbon pre-lithium composite precursor.

Abstract: A semiconductor structure includes: a substrate and a fin protruding from the substrate. The fin comprises a first semiconductive layer over the substrate, a second semiconductive layer over the first semiconductive layer, and a dielectric layer disposed between the first semiconductive layer and the second semiconductive layer and electrically isolated from the first semiconductive layer and the second semiconductive layer. The semiconductor structure further includes a gate electrode including: a first conductive portion extending along two opposite sidewalls of the first semiconductive layer and along an upper surface of the substrate; and a second conductive portion electrically isolated from the first conductive portion and extending along two opposite sidewalls of the second semiconductive layer and along an upper surface of the fin.

Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

Abstract: An element-doped silicon-carbon composite negative electrode material is provided. The negative electrode material comprises a plurality of element-doped silicon-carbon composite negative electrode material particles, and each them comprises an element-doped silicon nanoparticle, a first carbon coating layer and a second carbon coating layer. The element-doped silicon nanoparticle is a core, and the first carbon coating layer is coated on the element-doped silicon nanoparticle, the second carbon coating layer covers the first carbon coating layer. The dopant element comprises at least one of a group IIIA element, a group VA element and a transition metal element. A method of preparing the element-doped silicon-carbon composite negative electrode material is further provided.

Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

Abstract: A semiconductor structure includes a substrate and a fin protruding from the substrate along a first direction, wherein the fin includes a first semiconductive layer over the substrate, a second semiconductive layer over the first semiconductive layer along the first direction, and a dielectric layer disposed between the first semiconductive layer and the second semiconductive layer and electrically isolated from the first semiconductive layer and the second semiconductive layer. The semiconductor structure also includes a gate electrode including: a first conductive portion extending in a second direction different from the first direction and including an upper surface level with an upper surface of the first semiconductive layer; and a second conductive portion electrically isolated from the first conductive portion and including a bottom surface level with a bottom surface of the second semiconductive layer.

Abstract: A gas sensor for sensing a gas in a humid environment includes a first electrode layer, a second electrode layer that is spaced apart from the first electrode layer, and a gas sensing layer that electrically interconnects the first electrode layer and the second electrode layer. The gas sensing layer is made of a hygroscopic electrically insulating material.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a polysilicon structure around the superlattice structure, forming a source/drain opening within the superlattice structure, forming a first conductivity type S/D region within a first portion of the S/D opening, forming an isolation layer on the first conductivity type S/D region and within a second portion of the S/D opening, forming a second conductivity type S/D region on the isolation layer and within a third portion the S/D opening, and replacing the polysilicon structure and the second nanostructured layers with a gate structure that surrounds the first nanostructured layers. Materials of the first and second nanostructured layers are different from each other and the second conductivity type is different from the first conductivity type.

Abstract: The present disclosure describes a semiconductor device with substantially uniform gate regions and a method for forming the same. The method includes forming a fin structure on a substrate, the fin structure including one or more nanostructures. The method further includes removing a portion of the fin structure to expose an end of the one or more nanostructures and etching the end of the one or more nanostructures with one or more etching cycles. Each etching cycle includes purging the fin structure with hydrogen fluoride (HF), etching the end of the one or more nanostructures with a gas mixture of fluorine (F2) and HF, and removing an exhaust gas mixture including an etching byproduct. The method further includes forming an inner spacer in the etched end of the one or more nanostructures.