Abstract: A method for processing a network allocation vector (NAV) includes: terminating the receiving of a first radio frame when it is determined that a target receiving station of the first radio frame being received is not a first station; and updating an NAV of the first station or maintaining the NAV of the first station unchanged according to a remaining duration of the first radio frame and a first transmission opportunity duration carried in the first radio frame, where the remaining duration of the first radio frame is the transmission time used for transmitting the remaining part of the first radio frame after the receiving of the first radio frame is terminated. The technical solution solves the problem in the related art of collisions with hidden stations caused by an inaccurate NAV update in the existing art, thereby ensuring the accuracy of an NAV update and the fairness of transmission and channel contention, and reducing collisions among hidden stations.

Abstract: An overlay alignment mark located in a patterned wafer and a method for measuring overlay error are provided, the patterned wafer having a lower-layer pattern in a first layer thereof and an upper-layer pattern in a second layer thereof above the first layer, the overlay alignment mark comprising: a first pattern, which is a portion of the lower-layer pattern and comprises a pair of solid features formed in the first layer; and a second pattern, which is a portion of the upper-layer pattern and comprises two pairs of hollowed features formed in the second layer, with two imaginary lines connecting between geometric centers of respective pairs in the two pairs of hollowed features extending in two mutually orthogonal directions, respectively; an orthographic projection of the pair of solid features on the wafer at least partially overlaps with an orthographic projection of a respective pair of hollowed features on the wafer.

Abstract: Embodiments disclosed herein include a transistor and methods of making a transistor. In an embodiment, the transistor comprises a channel region and a gate structure over the channel region. In an embodiment, a first spacer is on a first end of the gate structure, and a second spacer is on a second end of the gate structure. In an embodiment, individual ones of the first spacer and the second spacer comprise a first layer with a first dielectric constant, and a second layer with a second dielectric constant that is higher than the first dielectric constant. In an embodiment, the transistor further comprises a source region adjacent to the first spacer, and a drain region adjacent to the second spacer.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer over a conductive interconnect line, the ILD layer having a trench therein, the trench exposing a portion of the conductive interconnect line. A dielectric liner layer is along a top surface of the ILD layer and along sidewalls of the trench, the dielectric liner layer having an opening therein, the opening over the portion of the conductive interconnect line. A conductive via structure is in the trench and between portions of the dielectric liner layer along the sidewalls of the trench, the conductive via structure having a portion extending vertically beneath the dielectric liner layer and in contact with the portion of the conductive interconnect line.

Abstract: Stacked thermal process chamber module for remote radiative heating of semiconductor device workpieces. A stacked thermal process module may include a stack of thermal process chambers and one or more generators of electromagnetic radiation. The electromagnetic radiation may be transported from a generator remote from the process chambers through one or more waveguides, thereby minimizing the volume and/or cleanroom footprint of the stacked thermal process chamber module. A waveguide may terminate in a process chamber so that electromagnetic radiation delivered during a thermal process may be coupled into one or more materials of the workpiece. The radiative heating process may overcome many of the limitations of thermal process chambers that instead employ a local heat source located within a process chamber.

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Abstract: Stacked thermal process chamber module for remote radiative heating of semiconductor device workpieces. A stacked thermal process module may include a stack of thermal process chambers and one or more generators of electromagnetic radiation. The electromagnetic radiation may be transported from a generator remote from the process chambers through one or more waveguides, thereby minimizing the volume and/or cleanroom footprint of the stacked thermal process chamber module. A waveguide may terminate in a process chamber so that electromagnetic radiation delivered during a thermal process may be coupled into one or more materials of the workpiece. The radiative heating process may overcome many of the limitations of thermal process chambers that instead employ a local heat source located within a process chamber.

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Abstract: Non-planar transistor devices which include oxide isolation structures formed in semiconductor bodies thereof through the formation of an oxidizing catalyst layer on the semiconductor bodies followed by an oxidation process. In one embodiment, the semiconductor bodies may be formed from silicon-containing materials and the oxidizing catalyst layer may comprise aluminum oxide, wherein oxidizing the semiconductor body to form an oxide isolation zone forms a semiconductor body first portion and a semiconductor body second portion with the isolation zone substantially electrically separating the semiconductor body first portion and the semiconductor body second portion.

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Abstract: Bioluminescent imaging has proven to be a valuable tool for monitoring physiological and pathological activities at cellular and molecular levels in living small animals. Using biological techniques, target cells can be tagged with reporters which generate characteristic photons in a wide spectrum covering the infra-red range. Part of the diffused light can reach the body surface of a subject/specimen (e.g., a small animal), be separated into several spectral bands using optical means, and collected by a sensitive camera. Systems and methods are disclosed herein for multi-spectral bioluminescence tomography (MBLT), in which an image of an underlying 3D bioluminescent source distribution is synergistically reconstructed from spectrally resolved datasets externally measured. This MBLT process involves two or multiple imaging modalities that produce structural information of the object and optical properties of the object as well to enable and improve the quality of MBLT.

Abstract: Bioluminescent imaging has proven to be a valuable tool for monitoring physiological and pathological activities at cellular and molecular levels in living small animals. Using biological techniques, target cells can be tagged with reporters which generate characteristic photons in a wide spectrum covering the infra-red range. Part of the diffused light can reach the body surface of a subject/specimen (e.g., a small animal), be separated into several spectral bands using optical means, and collected by a sensitive camera. Systems and methods are disclosed herein for multi-spectral bioluminescence tomography (MBLT), in which an image of an underlying 3D bioluminescent source distribution is synergistically reconstructed from spectrally resolved datasets externally measured. This MBLT process involves two or multiple imaging modalities that produce structural information of the object and optical properties of the object as well to enable and improve the quality of MBLT.

Abstract: An amorphous or polycrystalline silicon film that does not facilitate the reduction of neighboring oxide may be deposited during semiconductor device/integrated circuit fabrication.

Abstract: L-shaped spacers for use adjacent to the vertical sidewalls of gate electrodes in the manufacture of MOS integrated circuits are described along with methods of fabricating such structures that do not require any additional cost compared to conventional manufacturing processes. A spacer is formed as a tri-layer of silicon oxide/silicon nitride/silicon oxide deposited in- situ at low temperature using a conventional furnace and a bis(tertiarybutylamino) silane chemistry deposition. The spacer has the same performance as a conventional spacer during deep source/drain (S/D) implants. Prior to a cleaning operation which precedes silicidation, the top oxide layer is removed leading to improved gap-fill characteristics. The upper oxide may to removed before deep S/D implantation to further achieve reduction of series resistance.

Abstract: A method of processing a semiconductor substrate, comprising the steps of: heating a substance within a first chamber, at a selected temperature which is above the minimum decomposition temperature of the substance, to cause decomposition of the substance into a predetermined gas; cooling the gas to below the minimum decomposition temperature of the substance; transporting the gas from the first chamber to a second chamber; and exposing a semiconductor substrate, located in the second chamber, to the cooled gas.