Abstract: An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss.

Abstract: A projection device includes a shell, a lens, two first ribs, two second ribs, and a sliding cover. The shell has a top plate, a left sidewall, and a right sidewall, the top plate is respectively connected to the left sidewall and the right sidewall, and the top plate has an opening. The lens is disposed in the shell and exposed by the opening. The two first ribs are disposed on the top plate, extending directions of the two first ribs are perpendicular to the left sidewall and the right sidewall, and the opening is disposed between the two first ribs. The sliding cover is slidably disposed on the shell for covering the opening. The two second ribs are disposed on a top cover body of the sliding cover, and one of the two second ribs is located between the two first ribs.

Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

Abstract: An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.

Abstract: A device includes a first power rail for a first power domain and a second power rail for a second power domain. A first circuit block is connected to the first power rail and a second circuit block is connected to the second power rail. The first and second circuit blocks are both connected to a virtual VSS terminal. A footer circuit is connected between the virtual VSS terminal and a ground terminal, and the footer circuit is configured to selectively control a connection between the virtual VSS terminal and the ground terminal.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.

Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.

Abstract: A plug connector having a protective member replacing a gold finger on a circuit board includes an insulation base, a cable terminal block, and a grip. The insulation base includes a top wall, a bottom wall, and two side walls. The cable terminal block includes at least one cable including multiple conductors. The circuit board includes a contact section and a solder section, and the width of the solder section is greater than the width of the contact section. Two stopping and grounding parts are respectively formed on both sides of the solder section adjacent to the contact section. The circuit board includes multiple conductive pads on a surface of the contact section and multiple solder pads on a surface of the solder section. The conductors of the cable are separately soldered to solder pads. The protective member is clipped to the contact section of the circuit board.

Abstract: A plug connector having a protective member replacing a gold finger on a circuit board includes an insulation base, a cable terminal block, and a grip. The insulation base includes a top wall, a bottom wall, and two side walls. The cable terminal block includes at least one cable including multiple conductors. The circuit board includes a contact section and a solder section, and the width of the solder section is greater than the width of the contact section. Two stopping and grounding parts are respectively formed on both sides of the solder section adjacent to the contact section. The circuit board includes multiple conductive pads on a surface of the contact section and multiple solder pads on a surface of the solder section. The conductors of the cable are separately soldered to solder pads. The protective member is clipped to the contact section of the circuit board.

Abstract: A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and wetting the surface of the first barrier layer. The above layers are then patterned into a gate, and a source/drain is formed in the substrate beside the gate.

Abstract: A metal-gate complementary metal-oxide-semiconductor (CMOS) device is disclosed. The CMOS device includes a PMOS transistor formed on a first area of a substrate and a NMOS transistor formed on a second area of the substrate and being coupled to the PMOS transistor. The PMOS transistor includes a first gate stack consisting of a first dielectric layer, a first single-layer metal directly stacked on the first dielectric layer, and a first conductive capping layer directly stacked on the first single-layer metal. The NMOS transistor includes a second gate stack consisting of a second dielectric layer, a second single-layer metal directly stacked on the second dielectric layer, and a second conductive capping layer directly stacked on the second single-layer metal.

Abstract: A MOS transistor including a substrate, a gate dielectric layer on the substrate, a stacked gate on the gate dielectric layer, and a source/drain in the substrate beside the stacked gate is provided. In particular, the stacked gate includes, from bottom to top, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer, wherein the work-function-dominating layer includes a metallic material.

Abstract: A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and wetting the surface of the first barrier layer. The above layers are then patterned into a gate, and a source/drain is formed in the substrate beside the gate.

Abstract: A metal-gate complementary metal-oxide-semiconductor (CMOS) device is disclosed. The CMOS device includes a PMOS transistor formed on a first area of a substrate and a NMOS transistor formed on a second area of the substrate and being coupled to the PMOS transistor. The PMOS transistor includes a first gate stack consisting of a first dielectric layer, a first single-layer metal directly stacked on the first dielectric layer, and a first conductive capping layer directly stacked on the first single-layer metal. The NMOS transistor includes a second gate stack consisting of a second dielectric layer, a second single-layer metal directly stacked on the second dielectric layer, and a second conductive capping layer directly stacked on the second single-layer metal.

Abstract: A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and wetting the surface of the first barrier layer. The above layers are then patterned into a gate, and a source/drain is formed in the substrate beside the gate.