Abstract: A plug connector having a protective member replacing a gold finger on a circuit board includes an insulation base, a cable terminal block, and a grip. The insulation base includes a top wall, a bottom wall, and two side walls. The cable terminal block includes at least one cable including multiple conductors. The circuit board includes a contact section and a solder section, and the width of the solder section is greater than the width of the contact section. Two stopping and grounding parts are respectively formed on both sides of the solder section adjacent to the contact section. The circuit board includes multiple conductive pads on a surface of the contact section and multiple solder pads on a surface of the solder section. The conductors of the cable are separately soldered to solder pads. The protective member is clipped to the contact section of the circuit board.

Abstract: A plug connector having a protective member replacing a gold finger on a circuit board includes an insulation base, a cable terminal block, and a grip. The insulation base includes a top wall, a bottom wall, and two side walls. The cable terminal block includes at least one cable including multiple conductors. The circuit board includes a contact section and a solder section, and the width of the solder section is greater than the width of the contact section. Two stopping and grounding parts are respectively formed on both sides of the solder section adjacent to the contact section. The circuit board includes multiple conductive pads on a surface of the contact section and multiple solder pads on a surface of the solder section. The conductors of the cable are separately soldered to solder pads. The protective member is clipped to the contact section of the circuit board.

Abstract: A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and wetting the surface of the first barrier layer. The above layers are then patterned into a gate, and a source/drain is formed in the substrate beside the gate.

Abstract: A metal-gate complementary metal-oxide-semiconductor (CMOS) device is disclosed. The CMOS device includes a PMOS transistor formed on a first area of a substrate and a NMOS transistor formed on a second area of the substrate and being coupled to the PMOS transistor. The PMOS transistor includes a first gate stack consisting of a first dielectric layer, a first single-layer metal directly stacked on the first dielectric layer, and a first conductive capping layer directly stacked on the first single-layer metal. The NMOS transistor includes a second gate stack consisting of a second dielectric layer, a second single-layer metal directly stacked on the second dielectric layer, and a second conductive capping layer directly stacked on the second single-layer metal.

Abstract: A MOS transistor including a substrate, a gate dielectric layer on the substrate, a stacked gate on the gate dielectric layer, and a source/drain in the substrate beside the stacked gate is provided. In particular, the stacked gate includes, from bottom to top, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer, wherein the work-function-dominating layer includes a metallic material.

Abstract: A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and wetting the surface of the first barrier layer. The above layers are then patterned into a gate, and a source/drain is formed in the substrate beside the gate.

Abstract: A metal-gate complementary metal-oxide-semiconductor (CMOS) device is disclosed. The CMOS device includes a PMOS transistor formed on a first area of a substrate and a NMOS transistor formed on a second area of the substrate and being coupled to the PMOS transistor. The PMOS transistor includes a first gate stack consisting of a first dielectric layer, a first single-layer metal directly stacked on the first dielectric layer, and a first conductive capping layer directly stacked on the first single-layer metal. The NMOS transistor includes a second gate stack consisting of a second dielectric layer, a second single-layer metal directly stacked on the second dielectric layer, and a second conductive capping layer directly stacked on the second single-layer metal.

Abstract: A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and wetting the surface of the first barrier layer. The above layers are then patterned into a gate, and a source/drain is formed in the substrate beside the gate.