Abstract: A mixer for use in a transceiver comprises an LO switching pair and a folded transconductor. The mixer can be used as an upconversion or down conversion mixer and provides increased headroom and linearity, while still reducing current consumption. The mixer can be configured for differential inputs and outputs and the folded transconductor can comprises a MOSFET differential pair.

Abstract: An automatic quadrature phase compensation system comprises an on-chip analog phase sense circuit capable of detecting small differences in quadrature phase error and providing a corresponding DC voltage, a voltage-controlled or programmable phase delay circuit to implement quadrature phase error correction, and a feedback system or compensation engine used to process the sensed error voltage and apply a corresponding correction signal to the adjustable phase delay.

Abstract: An automatic quadrature phase compensation system comprises an on-chip analog phase sense circuit capable of detecting small differences in quadrature phase error and providing a corresponding DC voltage, a voltage-controlled or programmable phase delay circuit to implement quadrature phase error correction, and a feedback system or compensation engine used to process the sensed error voltage and apply a corresponding correction signal to the adjustable phase delay.

Abstract: A continuous time delta-sigma analog to digital converter is disclosed. A summing junction receives an input analog signal to be digitized and a feedback signal. A loop filter receives the combined signals from the summing junction, and a course analog to digital converter converts the combined signal to a multi-bit digital number. A sin DAC provides a feedback signal to the summing junction, by reconverting the multi-bit digital signal to an analog signal. The sin DAC produces a linear output signal having a reduced phase jitter, resulting in a lower noise floor for the multi-digital signal. The sin DAC may be an NRZ sin DAC which avoids stringent linearity requirements on the summing junction.

Abstract: A continuous time delta-sigma analog to digital converter is disclosed. A summing junction receives an input analog signal to be digitized and a feedback signal. A loop filter receives the combined signals from the summing junction, and a course analog to digital converter converts the combined signal to a multi-bit digital number. A sin DAC provides a feedback signal to the summing junction, by reconverting the multi-bit digital signal to an analog signal. The sin DAC produces a linear output signal having a reduced phase jitter, resulting in a lower noise floor for the multi-digital signal. The sin DAC may be an NRZ sin DAC which avoids stringent linearity requirements on the summing junction.