Abstract: An automatic industry classification method comprises: determining a scope of target patents, defining a target industry tree; generating marks on the target industry tree; performing a rough classification for the target patents by using the marks; performing a fine classification for the target patents according to a result of the rough classification. The automatic industry classification method and system provided by the present invention uses a transductive learning method, so that full mining of small annotation quantity information is realized. The automatic industry classification method and system uses information of IPC, so that information dimension is enriched, and calculation amount needed in the classification is reduced. The automatic industry classification method and system further uses the hierarchical vectors generated by the abstract, the claims and the description, so that the information of word order relation is reserved, and the patent text is deeply mined.

Abstract: A patent evaluation method and system thereof are provided. The method includes collecting patent documents, and further includes the following steps: generating technical points and patent-affiliated technical points; generating technical clusters and patent-affiliated cluster; performing a patent evaluation in each of the technical clusters. The patent evaluation method and system proposed in the present invention aggregates the patents in a technical cluster mode through natural language processing and complex network algorithms, gives patents scientific and technological attributes, and places the patents in a global same industry for evaluation.

Abstract: An automatic industry classification method comprises: determining a scope of target patents, defining a target industry tree; generating marks on the target industry tree; performing a rough classification for the target patents by using the marks; performing a fine classification for the target patents according to a result of the rough classification. The automatic industry classification method and system provided by the present invention uses a transductive learning method, so that full mining of small annotation quantity information is realized. The automatic industry classification method and system uses information of IPC, so that information dimension is enriched, and calculation amount needed in the classification is reduced. The automatic industry classification method and system further uses the hierarchical vectors generated by the abstract, the claims and the description, so that the information of word order relation is reserved, and the patent text is deeply mined.

Abstract: A patent evaluation method and system thereof are provided. The method includes collecting patent documents, and further includes the following steps: generating technical points and patent-affiliated technical points; generating technical clusters and patent-affiliated cluster; performing a patent evaluation in each of the technical clusters. The patent evaluation method and system proposed in the present invention aggregates the patents in a technical cluster mode through natural language processing and complex network algorithms, gives patents scientific and technological attributes, and places the patents in a global same industry for evaluation.

Abstract: A semiconductor device and method for forming a semiconductor device are presented. The method includes providing a patterned reticle having a pattern perimeter defined by active and dummy patterns. The dummy patterns include dummy structures modified according to a density equation. The patterned reticle is used to pattern a resist layer on a substrate with a device layer. An etch is performed to pattern the device layer using the patterned resist layer. Additional processing is performed to complete formation of the device.

Abstract: A method for synchronizing a first circuit to an electro-optical sensor is disclosed. The method generally includes steps (A) to (D). Step (A) may generate with the first circuit a configuration signal that conveys a request to capture at least one frame of a plurality of periodic frames. Step (B) may receive the periodic frames at a second circuit from the electro-optical sensor. Step (C) may discard a first frame of the periodic frames where the first frame precedes the request. Step (D) may store a plurality of active pixels in a second frame of the periodic frames in a memory where the second frame follows the request. The second circuit is generally a hardware implementation.

Abstract: A semiconductor device and method for forming a semiconductor device are presented. The method includes providing a patterned reticle having a pattern perimeter defined by active and dummy patterns. The dummy patterns include dummy structures modified according to a density equation. The patterned reticle is used to pattern a resist layer on a substrate with a device layer. An etch is performed to pattern the device layer using the patterned resist layer. Additional processing is performed to complete formation of the device.

Abstract: A method for synchronizing a first circuit to an electro-optical sensor is disclosed. The method generally includes steps (A) to (D). Step (A) may generate with the first circuit a configuration signal that conveys a request to capture at least one frame of a plurality of periodic frames. Step (B) may receive the periodic frames at a second circuit from the electro-optical sensor. Step (C) may discard a first frame of the periodic frames where the first frame precedes the request. Step (D) may store a plurality of active pixels in a second frame of the periodic frames in a memory where the second frame follows the request. The second circuit is generally a hardware implementation.

Abstract: A method for moving data in a memory system of a cascading region-based filter is disclosed. The method generally includes steps (A) to (C). Step (A) may load a first portion of the data from a buffer to the memory system at a start of a given cycle using a control circuit. The memory system generally has multiple first memories. A first region of a particular first memory may receive the first portion of data. Step (B) may copy the data in a second region of the particular first memory to a third region of the particular first memory at an end of the given cycle. Step (C) may copy the data in an output region of the particular first memory to an input region of a next first memory at the end of the given cycle. The output region generally overlaps both the first region and the second region.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.

Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

Abstract: An integrated circuit structure includes a semiconductor substrate and a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor is in contact with the thyristor.

Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

Abstract: An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a gate dielectric layer over the semiconductor substrate. The gate dielectric layer is formed in a plurality of thicknesses in a plurality of devices regions over the semiconductor substrate. A second dielectric layer is formed over at least one of the devices regions. A third dielectric layer is formed over at least a portion of the second dielectric layer. Ion traps are then selectively implanted in portions of the second dielectric layer.

Abstract: An integrated circuit structure includes a semiconductor substrate and a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor is in contact with the thyristor.