Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.

Abstract: Disclosed is an approach for performing pattern classification for electronic designs. One advantage of this approach is that it can use fast pattern matching techniques to classify both patterns and markers based on geometric similarity. In this way, the large number of markers and hotspots that typically are identified within an electronic design can be subsumed and compressed into a much smaller set of pattern families. This significantly reduced the number of patterns that must be individually analyzed, which considerably reduces the quantity of system resources and time needed to analyze and verify a circuit design.

Abstract: Disclosed is an approach for performing pattern classification for electronic designs. One advantage of this approach is that it can use fast pattern matching techniques to classify both patterns and markers based on geometric similarity. In this way, the large number of markers and hotspots that typically are identified within an electronic design can be subsumed and compressed into a much smaller set of pattern families. This significantly reduced the number of patterns that must be individually analyzed, which considerably reduces the quantity of system resources and time needed to analyze and verify a circuit design.

Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.

Abstract: A system and method for integrated circuit design layout processing are disclosed to partition and extract the layout and optimize settings individually for an optimal solution to provide manufacturability enhancement. The integrated circuit design layout system and method are provided for splitting an integrated circuit layout into independent portions or pieces, which can be processed independently and reassembled together, based on prior information about the layout itself, or predefined data processing flow, which are commonly available at the time of processing individual layouts. The integrated circuit design layout system and method split the layout based on hierarchal geometry segregation rules that are derived from the layout data information or data processing flow.

Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.

Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.

Abstract: A system and method for integrated circuit design layout processing are disclosed to partition and extract the layout and optimize settings individually for an optimal solution to provide manufacturability enhancement. The integrated circuit design layout system and method are provided for splitting an integrated circuit layout into independent portions or pieces, which can be processed independently and reassembled together, based on prior information about the layout itself, or predefined data processing flow, which are commonly available at the time of processing individual layouts. The integrated circuit design layout system and method split the layout based on hierarchal geometry segregation rules that are derived from the layout data information or data processing flow.

Abstract: One embodiment of the invention provides a system that facilitates optical proximity correction for alternating aperture phase shifting designs. During operation, the system receives a layout, which includes a complementary mask and a phase shifting mask. A subset of trim features on the complementary mask that are designed to protect the dark areas left unexposed by the phase shifting mask are adjusted first using a rules-based optical proximity correction process. This is then supplemented by a model-based correction to the phase shifters, Additionally, the portions of the trim that are co-extensive with the original layout can be corrected, e.g. at the time of the correction of the complementary mask using either rule or model based corrections.

Abstract: One embodiment of the invention provides a system that facilitates optical proximity correction for alternating aperture phase shifting designs. During operation, the system receives a layout, which includes a complementary mask and a phase shifting mask. A subset of trim features on the complementary mask that are designed to protect the dark areas left unexposed by the phase shifting mask are adjusted first using a rules-based optical proximity correction process. This is then supplemented by a model-based correction to the phase shifters, Additionally, the portions of the trim that are co-extensive with the original layout can be corrected, e.g. at the time of the correction of the complementary mask using either rule or model based corrections.

Abstract: A method of combustion synthesis is provided wherein a relatively low field or voltage is applied to a precursor material prior to ignition. The field is at a voltage level effective to energize the material such that a combustion wave is propagated in a controlled manner through the material and without substantial Joule heating prior to ignition of the material, but below voltage levels necessary to initiate combustion. The precursor material, typically comprising a mixture of components which contain stoichiometric amounts of the elements in the desired final product in powder form, is compressed to form a compact having a desired relative density. This compact is subjected to an electric field or voltage at a suitable energy level to achieve the desired energizing of the material. The thus-treated compact is then ignited at a suitable location by, e.g., radiative energy applied from an ignition means.