Patents by Inventor Wei-Peng Wang

Wei-Peng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153901
    Abstract: A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 9, 2024
    Inventors: Yu-Hung Lin, Han-Jong Chia, Wei-Ming Wang, Kuo-Chung Yee, Chen Chen, Shih-Peng Tai
  • Publication number: 20240128178
    Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.
    Type: Application
    Filed: February 8, 2023
    Publication date: April 18, 2024
    Inventors: Yu-Hung LIN, Wei-Ming WANG, Su-Chun YANG, Jih-Churng TWU, Shih-Peng TAI, Kuo-Chung YEE
  • Publication number: 20240113034
    Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.
    Type: Application
    Filed: February 8, 2023
    Publication date: April 4, 2024
    Inventors: Yu-Hung LIN, Wei-Ming WANG, Chih-Hao YU, PaoTai HUANG, Pei-Hsuan LO, Shih-Peng TAI
  • Publication number: 20240096830
    Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Yi Huang, Yu-Hung Lin, Wei-Ming Wang, Chen Chen, Shih-Peng Tai, Kuo-Chung Yee
  • Patent number: 10909948
    Abstract: A ubiquitous auto calibration device is provided, which includes microcontroller unit, flex bus, image receiver image processing module, and an image output unit. The microcontroller unit is provided for receiving the electronic signal and performing a self-adjusting process to the electronic signal. The flex bus is connected with the microcontroller unit, and is provided for transmitting the electronic signal to the image processing module after performing the self-adjusting process. The image receiver is provided for receiving the image signal from the image receiving interface. The image processing module is provided for performing an image calibration process to the image signal, so that the image signal can obey the color temperature standard, Gamma value, uniformity and color gamut standards when the panel outputs the image signal.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: February 2, 2021
    Assignee: Diva Laboratories, Ltd.
    Inventors: Chih-An Chen, Wei-Peng Wang, Ching-Min Huang, Tzu-Hui Lee, Chuan-Ling Peng, Chi-Chou Huang, Huei-Jiun Li, Mei-Chuan Ku
  • Publication number: 20200365113
    Abstract: A ubiquitous auto calibration device is provided, which includes microcontroller unit, flex bus, image receiver image processing module, and an image output unit. The microcontroller unit is provided for receiving the electronic signal and performing a self-adjusting process to the electronic signal. The flex bus is connected with the microcontroller unit, and is provided for transmitting the electronic signal to the image processing module after performing the self-adjusting process. The image receiver is provided for receiving the image signal from the image receiving interface. The image processing module is provided for performing an image calibration process to the image signal, so that the image signal can obey the color temperature standard, Gamma value, uniformity and color gamut standards when the panel outputs the image signal.
    Type: Application
    Filed: August 30, 2019
    Publication date: November 19, 2020
    Inventors: Chih-An CHEN, Wei-Peng WANG, Ching-Min HUANG, Tzu-Hui LEE, Chuan-Ling PENG, Chi-Chou HUANG, Huei-Jiun LI, Mei-Chuan KU
  • Patent number: 7830652
    Abstract: A monitor correction apparatus and a monitor having the same are provided. The monitor having the monitor correction apparatus includes a display panel and a first frame. The first frame covers a perimeter of the display panel and defines a display area. The monitor correction apparatus includes a front bezel that is integrally formed with the first frame and covers a part of the display area. Moreover, the monitor correction apparatus includes guide pins that are formed inside the first frame and near the front bezel. The monitor correction apparatus also includes a flexible printed circuit board which has at least one guide hole to be inserted by the guide pins. One end of the flexible printed circuit board extends into the front bezel. An optical sensor is disposed on the flexible printed circuit board and inside the front bezel and has an optical signal receiving zone.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: November 9, 2010
    Assignee: Chi Lin Technology Co., Ltd
    Inventors: Tsung-Hsien Su, Tsung-Ho Chen, Kou-Lin Chou, Wei-Peng Wang
  • Publication number: 20100134960
    Abstract: A monitor correction apparatus and a monitor having the same are provided. The monitor having the monitor correction apparatus includes a display panel and a first frame. The first frame covers a perimeter of the display panel and defines a display area. The monitor correction apparatus includes a front bezel that is integrally formed with the first frame and covers a part of the display area. Moreover, the monitor correction apparatus includes guide pins that are formed inside the first frame and near the front bezel. The monitor correction apparatus also includes a flexible printed circuit board which has at least one guide hole to be inserted by the guide pins. One end of the flexible printed circuit board extends into the front bezel. An optical sensor is disposed on the flexible printed circuit board and inside the front bezel and has an optical signal receiving zone.
    Type: Application
    Filed: March 23, 2009
    Publication date: June 3, 2010
    Inventors: Tsung-Hsien SU, Tsung-Ho Chen, Kou-Lin Chou, Wei-Peng Wang