Abstract: A capacitor structure includes two electrodes arranged oppositely and a dielectric layer located between the two electrodes, wherein the dielectric layer includes at least two perovskite layers stacked; an amorphous layer is provided between every two adjacent perovskite layers; two outermost perovskite layers of the at least two perovskite layers are in contact with the two electrodes, respectively.

Abstract: A method for forming a storage node contact structure and semiconductor structure are provided. The method includes providing a substrate having a surface on which bit line structures are formed; forming a groove at a part, corresponding to an active region, of bottom of the contact hole; and growing a silicon crystal from the groove in the contact hole by using an epitaxial growth process, and controlling growth rates of the silicon crystal in a first and second directions in a growth process to enable the growth rate of the silicon crystal in the first direction to be greater than the growth rate of the silicon crystal in the second direction at beginning of growth and enable the growth rate of the silicon crystal in the first direction to be equal to the growth rate of the silicon crystal in the second direction at end of the growth.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base including a first region and a second region, where a plurality of active pillars are arranged at intervals in the base located in the first region; forming a first dielectric layer on the base, where the first dielectric layer covers the plurality of active pillars; forming a first mask layer with a first mask pattern on the first dielectric layer; forming a second mask layer with a second mask pattern on the first mask layer; forming a third mask layer with a third mask opening, where the third mask opening is used to expose the first region; and removing part of the first dielectric layer by using the first mask layer, the second mask layer, and the third mask layer as a mask.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of memory cells located on a substrate. Each of the plurality of memory cells includes a transistor and a capacitor. The capacitor is electrically connected to the transistor. The capacitor includes a body portion, and at least one extension portion located on a side surface of the body portion, and the at least one extension portion is electrically connected to the body portion.

Abstract: A semiconductor structure, a method for manufacturing a semiconductor structure, and a memory are provided. The semiconductor structure includes a substrate, a plurality of active pillars arranged above the substrate, a storage structure, and a plurality of transistors. The active pillars are arranged in an array in a first direction and in a second direction. Each active pillar includes a first sub active pillar and a second sub active pillar arranged on the first sub active pillar. The first direction and the second direction intersect with each other and are both parallel to a top surface of the substrate. A material of the first sub active pillar includes a first element, and resistivity of the first sub active pillar including the first element is less than resistivity of the first sub active pillar absence of the first element. The storage structure covers a sidewall of the first sub active pillar.

Abstract: Embodiments relate to a three-dimensional semiconductor structure and a formation method thereof. The three-dimensional semiconductor structure includes: a substrate; and a device structure positioned on a top surface of the substrate. The device structure includes memory rows arranged at intervals along a first direction, each of the memory rows includes memory cells arranged at intervals along a second direction and a gap between adjacent two of the memory cells, and each of the memory cells includes a first stacked layer and a word line structure. The word line structure includes a first part positioned in the first stacked layer and a second part extending out of the first stacked layer along the first direction. At least adjacent two of the memory rows exist, and the second part of the memory cell in one of the memory rows extends into the gap in another one of the memory rows.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base and a capacitor structure. The base is provided with a capacitive contact structure. The capacitor structure is connected to the capacitive contact structure, and the capacitor structure includes a plurality of capacitor units stacked in a direction vertical to the capacitive contact structure.

Abstract: A method for forming a three-dimensional memory provided by embodiments includes: forming a substrate and a stacked layer, where the stacked layer includes first semiconductor layers and second semiconductor layers alternately stacked, a thickness of the second semiconductor layers is D1, the first semiconductor layers include a plurality of channel regions as well as a first region and a second region arranged on opposite two sides of each of the plurality of channel regions along a first direction, and the first direction is a direction parallel to the top surface of the substrate; forming a plurality of first openings respectively exposing the plurality of channel regions, a gap between adjacent two of the plurality of first openings along a second direction has a width D2, D1>D2; and depositing a conductive layer along the plurality of first openings.

Abstract: A semiconductor structure includes a substrate and a conductive structure located above the substrate. The conductive structure includes a plurality of first conductive structures and second conductive structures that are spaced apart from each other and extend in a first direction. Lengths of the first conductive structures and lengths of the second conductive structures vary in steps. The lengths of the plurality of first conductive structures and the lengths of the plurality of second conductive structures vary in steps. The first conductive structures and the second conductive structures form Word Lines (WLs).

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate; patterning the substrate to form a substrate layer and a plurality of silicon pillars; forming an oxide layer on a surface of the substrate layer between the plurality of silicon pillars; forming an isolation structure on the oxide layer, gaps being provided between upper part of the isolation structure and the silicon pillars; forming a first conductive layer in the gaps; partially removing the isolation structure and retaining the isolation structure below the first conductive layer to form an isolation layer; and forming a dielectric layer and a second conductive layer on surfaces of the isolation layer, the oxide layer, the first conductive layer and the silicon pillars.

Abstract: Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure, relating to the field of semiconductor technology. The semiconductor structure includes a substrate, a capacitor structure, a transistor structure, a bit line and a word line; and the substrate includes a semiconductor layer and a spacer. The capacitor structure is arranged on the substrate, and the spacer is positioned between the capacitor structure and at least a part of the semiconductor layer. The transistor structure and the word line are arranged on a side of the capacitor structure distant from the substrate, one of a source and a drain of the transistor structure is electrically connected to the capacitor structure, a gate of the transistor structure is electrically connected to the word line, and other one of the source and the drain of the transistor structure is electrically connected to the bit line.

Abstract: A semiconductor structure includes: a plurality of transistors located in a semiconductor layer; each of the transistors including a semiconductor body extending in a first direction and a gate structure covering at least one side surface of the semiconductor body; the first direction being a thickness direction of the semiconductor layer; a plurality of conductive pillars, each of the conductive pillars being located on a top surface of a corresponding semiconductor body and being in direct contact with the corresponding semiconductor body; a memory structure covering the plurality of conductive pillars.

Abstract: A memory device and a manufacturing method therefor. A film-stack structure is formed on a substrate, the film-stack structure includes sacrificial layers and active layers alternately stacked in a first direction. Part of the film-stack structure located in a first area is removed. A plurality of first grooves spaced apart from each other and extend in a second direction are formed, where the substrate is exposed from the first grooves to divide the active layers located in the first area into a plurality of active pillars spaced apart from each other. The sacrificial layers located in the first and second areas are removed. Part of the active layers located in the second area is removed, to form a plurality of step-shaped connection layers on an end of the second area away from the first area. Gate material layers are formed to cover the connection layers and the active pillars.

Abstract: A method for forming a memory includes the following operations: a substrate and a semiconductor layer located on the substrate are formed; the semiconductor layer is patterned to form a plurality of first isolation structures and channel regions, each first isolation structure includes a first through hole and a second through hole, and a first isolation pillar located between the first through hole and the second through hole; a first filling layer filling up the first through hole and the second through hole is formed; the first isolation pillar is removed to form a third through hole located in the first filling layer; a barrier layer filling up the third through hole is formed; the channel regions are exposed by removing the first filling layer; and a gate layer covering surfaces of the channel regions is formed.

Abstract: A method for manufacturing a semiconductor structure includes: forming first shallow trench isolation structures in a substrate, which isolate a plurality of active areas extending in first direction in the substrate, in which a first shallow trench isolation structure includes a sacrificial layer and a first dielectric layer stacked from bottom up in sequence; forming a plurality of word line isolation grooves in the substrate, in which a word line isolation groove is located above the sacrificial layer and extends in second direction; forming a second dielectric layer on sidewalls of the word line isolation groove, in which a pore penetrating to the substrate is provided inside the second dielectric layer; metallizing a lower part of an active area based on the pore to form a bit line extending in first direction; and removing the sacrificial layer based on the pore to form an air gap between adjacent bit lines.

Abstract: The present disclosure provides a capacitor and a manufacturing method thereof, and a semiconductor device. The capacitor includes a plurality of bottom electrodes, a top electrode structure, a dielectric layer, and a gap filling layer, where the top electrode structure is formed on one side of each of the plurality of bottom electrodes, one side of the dielectric layer is in contact with the plurality of bottom electrodes and the other side is in contact with the top electrode structure, and the gap filling layer fills remaining gaps between the plurality of bottom electrodes.

Abstract: A manufacturing method for capacitor structure includes: forming a dielectric layer on a first electrode, wherein the dielectric layer includes metal oxide layers doped with preset oxides, and part of the preset oxide and a metal oxide share oxygen atoms; and forming a second electrode on the dielectric layer, wherein the first electrode, the dielectric layer and the second electrode constitute a capacitor structure.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method of the semiconductor structure includes: providing a substrate, a plurality of spaced first trenches being formed in the substrate; forming a sacrificial layer in the first trenches and a first protective layer on the sacrificial layer, the sacrificial layer and the first protective layer filling up the first trenches, and the first protective layer in the first trenches being provided with etching holes penetrating through the first protective layer; removing the sacrificial layer with the etching holes to form air gaps; and carrying out a silicification reaction on the substrate between adjacent ones of the first trenches and close to bottoms of the first trenches to form bit lines (BLs) in the substrate, parts of side surfaces of the BLs being exposed in the air gaps.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method for forming the semiconductor structure includes the following operations. A base is provided, in which the base includes a substrate, a first semiconductor layer and a second semiconductor layer sequentially formed on one another. A plurality of first isolation structures spaced apart from each other and a plurality of second isolation structures spaced apart from each other are formed in the base. A channel layer is formed in the first semiconductor layer, in which a through hole is provided between the channel layer and each of two first isolation structures adjacent to the channel layer. A gate structure is formed in the through hole.

Abstract: Embodiments provide a semiconductor structure and a fabrication method thereof. The fabrication method includes: providing a substrate including a plurality of semiconductor layers arranged at intervals and an isolation layer positioned between adjacent two of the plurality of semiconductor layers, a given one of the plurality of semiconductor layers and the isolation layer being internally provided with trenches, and each of the trenches including a first region, a second region and a third region sequentially distributed; forming a sacrificial layer on an inner wall of the trench in the first region and the second region; forming an insulating layer filling up the trench on a surface of the sacrificial layer; removing the sacrificial layer in the second region, and removing the isolation layer of a first thickness to form voids surrounding the given semiconductor layer.