Patents by Inventor Weiqi Ding

Weiqi Ding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190337802
    Abstract: A process of producing chlorine gas by catalytic oxidation of hydrogen chloride including: incorporating an oxidizing agent such as ozone, hydrogen peroxide solution etc. into a gas stream of hydrogen chloride containing impurities, conducting oxidation pretreatment of the gas stream under the action of ultrasonic wave, such that the impurities contained in the gas stream are oxidized; where the gas stream obtained after the oxidation pretreatment is allowed to pass through a separating device, the oxidized impurities in the form of liquid and/or the oxidized impurities in the form of solid are removed from the gas stream so as to obtain a purified gas stream of hydrogen chloride, and thereafter the purified gas stream of hydrogen chloride is well mixed with a gas stream containing molecular oxygen, the resultant gas mixture is preheated to a reaction temperature, and then catalytically oxidized to produce chlorine gas.
    Type: Application
    Filed: June 22, 2019
    Publication date: November 7, 2019
    Inventors: Jiansheng Ding, Wuxi Luo, Bin Chen, Kunpeng Zhang, Weiqi Hua
  • Publication number: 20190291087
    Abstract: A catalyst for preparing chlorine gas by hydrogen chloride oxidation, comprising the following components calculated according to mass content based on the total weight of the catalyst: 0.5-20 wt % copper; 2-10 wt % manganese; 0.05-2 wt % boron; 0.01-3 wt % chromium; 0.1-10 wt % rare earth metal; 0.1-10 wt % potassium; and 3-15 wt % titanium; also comprising 0.02-1.1 wt % phosphorus; and 0.03-1.9 wt % iron; the carrier content is 55-90 wt %. In the case of a fluidized bed reactor, the present catalyst can achieve a one-way hydrogen chloride conversion rate of 80-85%. Almost all of the 0-1000 mg/kg of chlorinated benzene contained in hydrogen chloride gas can be converted into CO2 and H2O without generating polychlorinated benzene.
    Type: Application
    Filed: August 5, 2016
    Publication date: September 26, 2019
    Applicant: Wanhua Chemical Group Co., Ltd.
    Inventors: Hongke Zhang, Bo Zhou, Zhangwei Zai, Dan Xu, Yu Yao, Yanlong Xu, Dongke Zhao, Jingjing Yang, Jiansheng Ding, Weiqi Hua
  • Publication number: 20190201878
    Abstract: A supported catalyst used for synthesizing a polyether amine, and a manufacturing method of the catalyst. The catalyst comprises: a porous oxide as a support; Ni, Cu, Pd, and Rh as active components; and one or more of any of Zr, Cr, Mo, Fe, Zn, Sn, Bi, Ce, La, Hf, Sr, Sb, Mg, Be, Re, Ta, Ti, Sc, Ge and related metals as an auxiliary agent. The catalyst can be used in an amination reaction for a large molecular weight polyether polyol, and is particularly active and selective for an amination reaction of a low molecular weight polyether polyol. The catalyst has a simple and economic manufacturing technique and good potential for future applications.
    Type: Application
    Filed: August 24, 2016
    Publication date: July 4, 2019
    Applicant: Wanhua Chemical Group Co., Ltd.
    Inventors: Shujie Ren, Congying Zhang, Xin Li, Zhenguo Liu, Xiaolong Wang, Lei Tang, Zhipeng Liu, Zhanyu Gao, Jian Wu, Cong Wang, Yuan Li, Qingmei Jiang, Jinhong Song, Weiqi Hua, Hao Ding
  • Patent number: 10212498
    Abstract: Systems and methods are provided to improve flexibility of optical signal transmission between integrated circuit devices, and more specifically data utilization circuits. More specifically, the integrated circuit devices may include a data utilization circuit communicatively coupled to a field programmable optical array (FPOA). In some embodiments, the FPOA may convert an electrical signal received from the data utilization to an optical signal, route the optical signal to an optical channel, and multiplex the optical signal with other optical signals routed to the optical channel. Additionally or alternatively, the FPOA may de-multiplex a multiplexed optical signal based on wavelength, route an optical signal included in the multiplexed optical signal to an electrical channel, convert the optical signal into an electrical signal, and output the electrical signal to the data utilization circuit via an electrical channel.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: February 19, 2019
    Assignee: ALTERA CORPORATION
    Inventors: Mike Peng Li, Joel Martinez, Jon Long, Weiqi Ding, Sergey Yuryevich Shumarayev
  • Patent number: 9979403
    Abstract: A clocking arrangement for transceivers in an integrated circuit device includes a plurality of fractionally adjustable phase-locked loops. Each respective one of the fractionally adjustable phase-locked loops generates a respective transmit frequency for a respective one of the transceivers. There is a respective clock-data recovery module in a receive portion of each respective one of the transceivers, and each respective clock-data recovery module includes a respective fractionally adjustable frequency-lock loop. There is a reference clock input providing a reference clock for a plurality of the fractionally adjustable phase-locked loops and the fractionally adjustable frequency-lock loops. The reference clock input can be a sole reference clock input providing a reference clock for all of the adjustable phase-locked frequency-lock loops.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: May 22, 2018
    Assignee: ALTERA CORPORATION
    Inventor: Weiqi Ding
  • Patent number: 9960937
    Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 1, 2018
    Assignee: ALTERA CORPORATION
    Inventors: Weiqi Ding, Mengchi Liu, Wilson Wong, Sergey Y. Shumarayev
  • Publication number: 20180091181
    Abstract: One embodiment relates to a method of automated adaptation of a transmitter equalizer. A multi-dimensional search space of tap settings for the transmitter equalizer is divided into multiple single-dimensional search spaces, each single-dimensional search space being associated with a single tap of the transmitter equalizer. The multiple single-dimensional search spaces are searched in series, and a tap for a single-dimensional search space is set before searching a next single-dimensional search space. Another embodiment relates to a transceiver with adaptation circuitry configured to perform this method. Other embodiments, aspects, and features are also disclosed.
    Type: Application
    Filed: December 4, 2017
    Publication date: March 29, 2018
    Inventors: Donald Alderrou, Peng Li, Weiqi Ding
  • Patent number: 9876519
    Abstract: One embodiment relates to a method of automated adaptation of a transmitter equalizer. A multi-dimensional search space of tap settings for the transmitter equalizer is divided into multiple single-dimensional search spaces, each single-dimensional search space being associated with a single tap of the transmitter equalizer. The multiple single-dimensional search spaces are searched in series, and a tap for a single-dimensional search space is set before searching a next single-dimensional search space. Another embodiment relates to a transceiver with adaptation circuitry configured to implement the above-described method. Other embodiments, aspects, and features are also disclosed.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: January 23, 2018
    Assignee: Altera Corporation
    Inventors: Donald Alderrou, Peng Li, Weiqi Ding
  • Publication number: 20170230209
    Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventors: Weiqi Ding, Mengchi Liu, Wilson Wong, Sergey Y. Shumarayev
  • Patent number: 9680675
    Abstract: One embodiment relates to a method of automated adaptation of a transmitter equalizer. A multi-dimensional search space of tap settings for the transmitter equalizer is divided into multiple single-dimensional search spaces, each single-dimensional search space being associated with a single tap of the transmitter equalizer. The multiple single-dimensional search spaces are searched in series, and a tap for a single-dimensional search space is set before searching a next single-dimensional search space. Another embodiment relates to a transceiver with adaptation circuitry configured to implement the above-described method. Other embodiments, aspects, and features are also disclosed.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: June 13, 2017
    Assignee: Altera Corporation
    Inventors: Donald Alderrou, Peng Li, Weiqi Ding
  • Patent number: 9660846
    Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: May 23, 2017
    Assignee: Altera Corporation
    Inventors: Weiqi Ding, Mengchi Lui, Wilson Wong, Sergey Y. Shumarayev
  • Patent number: 9654123
    Abstract: One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Another embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit including a first strip of PLL circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 16, 2017
    Assignee: Altera Corporation
    Inventors: Tien Duc Pham, Sergey Shumarayev, Richard G. Cliff, Tim Tri Hoang, Weiqi Ding
  • Patent number: 9608728
    Abstract: Systems and methods are provided to improve flexibility of optical signal transmission between integrated circuit devices, and more specifically data utilization circuits. More specifically, the integrated circuit devices may include a data utilization circuit communicatively coupled to a field programmable optical array (FPOA). In some embodiments, the FPOA may convert an electrical signal received from the data utilization to an optical signal, route the optical signal to an optical channel, and multiplex the optical signal with other optical signals routed to the optical channel. Additionally or alternatively, the FPOA may de-multiplex a multiplexed optical signal based on wavelength, route an optical signal included in the multiplexed optical signal to an electrical channel, convert the optical signal into an electrical signal, and output the electrical signal to the data utilization circuit via an electrical channel.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: March 28, 2017
    Assignee: Altera Corporation
    Inventors: Mike Peng Li, Joel Martinez, Jon Long, Weiqi Ding, Sergey Yuryevich Shumarayev
  • Patent number: 9543965
    Abstract: An integrated circuit package includes an interposer with an embedded clock network formed by multiple clock trees. A die with first and second clock circuits is disposed over the interposer. At least one of the first and second clock trees is a resonant clock tree and both the first and second clock circuits may provide clock signals at different frequencies. The first clock circuit may provide clock signals at one frequency to a clock tree in the embedded clock network while the second clock circuit may provide clock signals at another frequency to another clock tree in the embedded clock tree network.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 10, 2017
    Assignee: Altera Corporation
    Inventor: Weiqi Ding
  • Patent number: 9479181
    Abstract: A clocking arrangement for transceivers in an integrated circuit device includes a plurality of fractionally adjustable phase-locked loops. Each respective one of the fractionally adjustable phase-locked loops generates a respective transmit frequency for a respective one of the transceivers. There is a respective clock-data recovery module in a receive portion of each respective one of the transceivers, and each respective clock-data recovery module includes a respective fractionally adjustable frequency-lock loop. There is a reference clock input providing a reference clock for a plurality of the fractionally adjustable phase-locked loops and the fractionally adjustable frequency-lock loops. The reference clock input can be a sole reference clock input providing a reference clock for all of the adjustable phase-locked frequency-lock loops.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: October 25, 2016
    Assignee: Altera Corporation
    Inventor: Weiqi Ding
  • Patent number: 9444656
    Abstract: One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit. The first signal path includes first equalization circuitry, and the second signal path includes second equalization circuitry. The path selector circuit is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: September 13, 2016
    Assignee: Altera Corporation
    Inventors: Weiqi Ding, Sergey Shumarayev, Peng Li, Sriram Narayan
  • Patent number: 9429625
    Abstract: An analog test network includes a conductor. The conductor is coupled to provide a first analog signal from a circuit under test to an analog-to-digital converter circuit. The analog-to-digital converter circuit is operable to generate a first digital signal based on the first analog signal. A control circuit is operable to generate a second digital signal based on the first digital signal. A digital-to-analog converter circuit is operable to generate a second analog signal based on the second digital signal. The conductor is coupled to provide the second analog signal from the digital-to-analog converter circuit to the circuit under test.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: August 30, 2016
    Assignee: Altera Corporation
    Inventors: Weiqi Ding, Sergey Shumarayev
  • Patent number: 9401189
    Abstract: Integrated circuits may include memory interface circuitry operable to communicate with system memory. The memory interface circuitry may receive data (DQ) and data strobe (DQS) signals from system memory during read operations. The memory interface circuitry may include startup calibration circuitry and runtime calibration circuitry. The startup calibration circuitry may be used upon device startup to perform a one-time data de-skew and DQ/DQS centering. The runtime calibration circuitry may include at least two data sampling circuits, a first of which is used in active mode to latch incoming data and a second of which is used in redundant mode to obtain data eye boundary information on a continuous basis. The received DQS signal may be adjusted based on the obtained eye boundary information so that DQS properly positioned within the data eye periodically or on an as-needed basis.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 26, 2016
    Assignee: Altera Corporation
    Inventors: Weiqi Ding, Warren Nordyke
  • Patent number: 9350530
    Abstract: One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Each PMA module includes multiple CDR circuits, receives multiple serial data signals, and outputs data from those signals in parallel form. The programmable clock network allows the reference clock signals to be selectively shared by the PMA modules and the multiple-purpose PLLs. Another embodiment relates to a method of providing clock signals for multiple purposes in an integrated circuit. Clock signals are generated by a plurality of multiple-purpose PLLs and are selectively distributed to PMA modules arranged at a side of the integrated circuit and to logic circuitry arranged in a core section of the integrated circuit. The clock signals are used by circuitry in the PMA modules for supporting a plurality of data communications channels. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: May 24, 2016
    Assignee: Altera Corporation
    Inventors: Tien Duc Pham, Sergey Shumarayev, Richard G. Cliff, Tim Tri Hoang, Weiqi Ding
  • Patent number: 9222972
    Abstract: An IC that includes a jitter generator, where the jitter generator is integral with the IC and generates non-intrinsic jitter, is provided. In one implementation, the non-intrinsic jitter is used to measure a characteristic of the IC. In one implementation, the non-intrinsic jitter is used to test jitter tolerance of the IC. In yet another implementation, the non-intrinsic jitter is used to test another IC coupled to the IC that includes the jitter generator.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: December 29, 2015
    Assignee: Altera Corporation
    Inventors: Weiqi Ding, Sergey Shumarayev, Mingde Pan, Peng Li, Masashi Shimanouchi