Patents by Inventor Weiqiang Ma

Weiqiang Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230156826
    Abstract: Various approaches for the integration and use of edge computing operations in satellite communication environments are discussed herein. For example, connectivity and computing approaches are discussed with reference to: identifying satellite coverage and compute operations available in low earth orbit (LEO) satellites, establishing connection streams via LEO satellite networks, identifying and implementing geofences for LEO satellites, coordinating and planning data transfers across ephemeral satellite connected devices, service orchestration via LEO satellites based on data cost, handover of compute and data operations in LEO satellite networks, and managing packet processing, among other aspects.
    Type: Application
    Filed: December 24, 2020
    Publication date: May 18, 2023
    Inventors: Stephen T. Palermo, Francesc Guim Bernat, Marcos E. Carranza, Kshitij Arun Doshi, Cesar Martinez-Spessot, Thijs Metsch, Ned M. Smith, Srikathyayani Srikanteswara, Timothy Verrall, Rita H. Wouhaybi, Yi Zhang, Weiqiang MA, Atul Kwatra
  • Publication number: 20220014608
    Abstract: Various approaches for the packet processing, and the use of templates for generating modification commands for packet processing, are discussed herein. In an example, operations performed by network packet processing circuitry include: obtaining a stream of packets; obtaining a packet modification template that provides at least one command to insert content within the packets and change the packets according to an output format of a network protocol; receiving parameters to modify the packet modification template; and applying the packet modification template to modify the packets. In further examples, application of the packet modification template is performed using multiple processing components arranged in parallel groups of serial pipelines, each of the serial pipelines applying a portion of the packet modification template within at least a first stage and a second stage in each of the serial pipelines.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Weiqiang Ma, Atul Kwatra, Stephen T. Palermo
  • Patent number: 9286125
    Abstract: A processing engine implementing job arbitration with ordering status is disclosed. A method of the disclosure includes receiving, by a job assigner communicably coupled to a plurality of processors, availability status from a plurality of job rings, availability status from the plurality of processors, and job entry completion status from an order manager, identifying, based on the received job entry completion status, a set of job rings from the plurality of job rings that do not exceed threshold conditions maintained by the job assigner, selecting, from the identified set of job rings, a job ring from which to pull a job entry for assignment, wherein the selecting is based on the received availability status of the plurality of job rings, and selecting, based on the received availability status of the plurality of processors, a processor to receive the assignment of the job entry for processing.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 15, 2016
    Assignee: INTEL CORPORATION
    Inventors: David A. Smiley, Naveen Lakkakula, Weiqiang Ma, Justin B. Diether, Nitin N. Garegrat
  • Publication number: 20140282579
    Abstract: A processing engine implementing job arbitration with ordering status is disclosed. A method of the disclosure includes receiving, by a job assigner communicably coupled to a plurality of processors, availability status from a plurality of job rings, availability status from the plurality of processors, and job entry completion status from an order manager, identifying, based on the received job entry completion status, a set of job rings from the plurality of job rings that do not exceed threshold conditions maintained by the job assigner, selecting, from the identified set of job rings, a job ring from which to pull a job entry for assignment, wherein the selecting is based on the received availability status of the plurality of job rings, and selecting, based on the received availability status of the plurality of processors, a processor to receive the assignment of the job entry for processing.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventors: David A. Smiley, Naveen Lakkakula, Weiqiang Ma, Justin B. Diether, Nitin N. Garegrat
  • Publication number: 20030204675
    Abstract: Briefly, in accordance with an embodiment of the invention, a method to retrieve information from a flash memory is provided, wherein the method includes enabling prefetching in the flash memory and identifying nonrequested information in the flash memory if prefetching is enabled.
    Type: Application
    Filed: April 29, 2002
    Publication date: October 30, 2003
    Inventors: Lance W. Dover, Weiqiang Ma, Brian R. Mears, Sean S. Eilert
  • Patent number: 6154502
    Abstract: Data represented by a received point which is not within a boundary of a signal constellation having a set of points is obtained by comparing the received point to less than all of the points on a boundary of the signal constellation. In an embodiment, the received point is compared to no more than two points on the boundary which have been predetermined to be the closest to the received point.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: November 28, 2000
    Assignee: Intel Corporation
    Inventors: Zdenek Brun, Weiqiang Ma
  • Patent number: 5940437
    Abstract: A system and method for limiting the processing load on a digital processor in a block processing modem that is receiving data that was generated from the digital to analog clock of the remote transmit modem having a frequency that may be different than the frequency of the analog to digital clock in the local receiving modem. The receiving modem includes a digital processor having a desired processing capacity reserved for block processing of L samples of data per block period, an analog to digital converter for converting the received data into samples, an interpolator and a buffer memory. The analog to digital converter outputs L-A samples per block and passes them to the interpolator, where A.gtoreq.1. The interpolator processes L-B samples per block and passes them on to the buffer, where B.gtoreq.0. The buffer passes L samples per block to the modem processor. If L samples are not available, the processor skips a cycle.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: August 17, 1999
    Assignee: Intel Corporation
    Inventor: Weiqiang Ma
  • Patent number: 5793804
    Abstract: A system and method for limiting the processing load on a digital processor in a block processing modem that is receiving data that was generated remotely using a clock having a frequency that may be different than the frequency of the clock in the receiving modem. The receiving modem includes a digital processor having a desired processing capacity reserved for block processing of L samples of data per block period, an analog to digital converter for the received data into samples, an interpolator and a buffer memory. The analog to digital converter outputs L-A samples per block and passes them to the interpolator, where A.gtoreq.1. The interpolator processes L-B samples per block and passes them on to the buffer, where B.gtoreq.0. The buffer passes L samples per block to the modem processor. If L samples are not available, the processor skips a cycle.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: August 11, 1998
    Assignee: Intel Corporation
    Inventor: Weiqiang Ma