Abstract: Provided are a signal emitting apparatus, a signal receiving apparatus a signal processing method and a display system, wherein a remote controller can be deformed by applying a force to it, and a remote controlling signal is transmitted to a display apparatus to perform image displaying. The signal emitting apparatus comprises: a first receiving unit configured to receive a deformation operation input by a user, wherein the signal emitting apparatus is deformed under the deformation operation to generate a deformation quantity; a signal generating unit configured to generate a control signal according to the deformation quantity; and a signal transmitting unit configured to transmit the control signal to the signal receiving apparatus.

Abstract: A wireless charging system is disclosed, comprising a receiver circuit and a transmitter circuit, wherein the wireless charging system further comprises: a voltage detector connected to a load located at a side of the receiver circuit, for detecting a voltage change on the load; a transmitter connected to the voltage detector, for receiving a signal representing the voltage change on the load from the voltage detector and transmitting the signal; a receiver for receiving the signal from the transmitter and providing the signal to the transmitter circuit; wherein the transmitter circuit comprises a variable voltage source for providing different output voltages to the receiver circuit based on the signal received from the receiver. A method for use in the wireless charging system is also disclosed.

Abstract: A method for manufacturing an insulated conductive material includes providing a continuous feed of a conductive material, a first continuous feed of insulating material above a top surface of the conductive strip, and a second continuous feed of insulating material below a bottom surface of the conductive strip. Portions of the first and second continuous feeds of insulating material are compressed against a portion of the conductive material. The portions of the first and second insulating material are cured to thereby provide a continuous feed of insulated conductive material.

Abstract: The present invention provides a hair testing device and a hair testing system. The hair testing device includes a data acquisition part and a transmitting part. The data acquisition part is configured to acquire hair-related data and send the acquired data to the transmitting part. The transmitting part is configured to receive the acquired data and transmit the acquired data to a data processing device which is capable of processing data. The hair testing device further includes a fixing part for fixing to hair, and the data acquisition part and the transmitting part are both located on the fixing part. The hair testing device provided by the present invention is capable of automatically acquiring hair-related data, and sending the acquired data to the data processing device for processing, so as to achieve automatic testing of hair quality.

Abstract: Provided are a signal emitting apparatus, a signal receiving apparatus, a signal processing method and a display system, wherein a remote controller can be deformed by applying a force to it, and a remote controlling signal is transmitted to a display apparatus to perform image displaying. The signal emitting apparatus comprises: a first receiving unit configured to receive a deformation operation input by a user, wherein the signal emitting apparatus is deformed under the deformation operation to generate a deformation quantity; a signal generating unit configured to generate a control signal according to the deformation quantity; and a signal transmitting unit configured to transmit the control signal to the signal receiving apparatus.

Abstract: A toolholder includes an absorber mass externally mounted to a body portion of the toolholder. A spacer is disposed within one or more recesses formed in a bottom wall of the absorber mass. One or more resilient members are disposed between the body portion and the absorber mass, and one or more resilient members are disposed between the absorber mass and the spacer. A clamping bolt passes through each spacer, through the absorber mass and is threaded into the body portion of the toolholder. A rigidity of the one or more resilient members can be selectively adjusted by the clamping bolts so as to tune the absorber mass for optimum dampening of vibration of the toolholder.

Abstract: A thermal cut-off device includes a plastic base, two electrodes, a temperature sensing element, and a plastic cover that fits over the base. The temperature sensing element is curved downward, and may be a bimetal or a trimetal. When the device is subject to an over-temperature condition, the orientation of the curve flips such that the temperature sensing element is then curved upward. When the temperature sensing element is curved upward, it lifts an arm of one of the electrodes, which severs the electrical connection between the electrodes. In this manner the device shuts off during an over-temperature condition in order to protect the circuit in which the device is installed. To prevent corrosion of the temperature sensing element, a first moisture insulation layer is applied to the outer surface of the thermal cut-off device. The moisture insulation layer may be an epoxy adhesive or a UV/visible light-cured adhesive or light/heat cured adhesive.

Abstract: A toolholder includes an absorber mass externally mounted to a body portion of the toolholder. A spacer is disposed within one or more recesses formed in a bottom wall of the absorber mass. One or more resilient members are disposed between the body portion and the absorber mass, and one or more resilient members are disposed between the absorber mass and the spacer. A clamping bolt passes through each spacer, through the absorber mass and is threaded into the body portion of the toolholder. A rigidity of the one or more resilient members can be selectively adjusted by the clamping bolts so as to tune the absorber mass for optimum dampening of vibration of the toolholder.

Abstract: A method and apparatus for performing template-based classification of a circuit design are disclosed. A template file is read that defines a plurality of channel-connected-region (CCR) templates. A graph is formatted for each of the CCR templates. A plurality of CCRs are identified based on a partitioned netlist file that defines a given circuit design. A graph is generated for each of the identified CCRs. A matching CCR template graph is identified for each generated CCR graph. The template file may further defines super-CCR templates, and a graph may be formatted for each of the super-CCR templates. All possible combinations of CCRs and previously-matched super-CCRs that are candidates to match the formatted super-CCR template graph may be determined in an interative manner, for each formatted super-CCR template graph. A determination may be made as to which of the candidate combinations actually match the formatted super-CCR template graph.

Abstract: A method and apparatus for performing template-based classification of a circuit design are disclosed. A template file is read that defines a plurality of channel-connected-region (CCR) templates. A graph is formatted for each of the CCR templates. A plurality of CCRs are identified based on a partitioned netlist file that defines a given circuit design. A graph is generated for each of the identified CCRs. A matching CCR template graph is identified for each generated CCR graph. The template file may further defines super-CCR templates, and a graph may be formatted for each of the super-CCR templates. All possible combinations of CCRs and previously-matched super-CCRs that are candidates to match the formatted super-CCR template graph may be determined in an interative manner, for each formatted super-CCR template graph. A determination may be made as to which of the candidate combinations actually match the formatted super-CCR template graph.

Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. the elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.

Abstract: A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. the elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.

Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.

Abstract: A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

Abstract: A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

Abstract: A system for estimating stage delay in an integrated circuit design includes steps of receiving as input an integrated circuit design including a single stage having at least two inputs, an output, and an interconnect connected to the output; calculating a separate interconnect delay for the interconnect as a function of an input ramptime for each of the inputs; adding a gate delay of each of the inputs to the separate interconnect delay calculated as a function of the input ramptime to estimate a stage delay for each of the inputs; and generating as output the stage delay for each of the inputs.

Abstract: A method of computing output delay in a mathematical model of an integrated circuit by sorting cells of original design of an the integrated circuit in a topological order. The original output delays for the sorted cells in the original design are computed in the topological order, to produce original output ramp times. The original output ramp times are propagated and original output delays are computed, and the original output ramp time and original output load for each cell is stored. The cells of the original design are modified to produce a modified design. For each modified cell in the topological order, a new output delay and a new output ramp time are computed and compared to the original output ramp time on the modified cell. When the new output ramp time substantially equals the original output ramp time for a modified cell, the calculations of the modified output ramp time for cells that are further down in the topological order are stopped.

Abstract: A system for estimating stage delay in an integrated circuit design includes steps of receiving as input an integrated circuit design including a single stage having at least two inputs, an output, and an interconnect connected to the output; calculating a separate interconnect delay for the interconnect as a function of an input ramptime for each of the inputs; adding a gate delay of each of the inputs to the separate interconnect delay calculated as a function of the input ramptime to estimate a stage delay for each of the inputs; and generating as output the stage delay for each of the inputs.

Abstract: A method of computing output delay in a mathematical model of an integrated circuit original design by sorting cells of the original design in a topological order. The original output delays for the cells in the original design are computed in the sorted order, to produce original output ramp times. The original output ramp times are propagated and original output delays are computed, and the original output ramp time and original output load for each cell is stored. The cells of the original design are modified to produce a modified design. For each modified cell in the topological order, a new output delay and a new output ramp time are computed and compared to the original output ramp time on the modified cell. When the new output ramp time substantially equals the original output ramp time for a modified cell, the calculations of the modified output ramp time for cells that are further down in the topological order are stopped.