Abstract: An SAR ADC and a conversion method, which include an SAR control logic circuit configured to control A/D conversion by: 1) sampling analog input signal for first time; 2) subjecting the sampled signal to conversions; 3) sampling analog input signal for another time; 4) subjecting the sampled signal in step 3) to conversion including: i) determining whether the lowest M bits of previous N-bit digital output signal are 1's or 0's, if so, looping back to step 2), otherwise, proceeding to step ii); ii) performing conversions on lowest M bits of new N-bit digital output signal, directly taking N-th to (M+1)-th bits of previous N-bit digital output signal as N-th to (M+1)-th bits of new N-bit digital output signal, and repeating steps 3) and 4) until the analog input signal is fully sampled and converted. Required cycles can be reduced resulting in higher conversion rate and lower power consumption.

Abstract: An SAR ADC and a conversion method are disclosed, which includes an SAR control logic circuit configured to control A/D conversion by steps: 1) sampling analog input signal for first time; 2) subjecting sampled signal to conversions; 3) sampling analog input signal for another time; 4) subjecting sampled signal in step 3) to conversion comprising: 41) determining whether the lowest M bits of previous N-bit digital output signal are 1's or 0's, if so, looping back to step 2), otherwise, proceeding to step 42); 42) performing conversions on lowest M bits of new N-bit digital output signal, directly taking N-th to (M+1)-th bits of previous N-bit digital output signal as N-th to (M+1)-th bits of new N-bit digital output signal, repeating steps 3) and 4) until analog input signal is fully sampled and converted. Required cycles can be reduced resulting in higher conversion rate and lower power consumption.

Abstract: A dummy pattern filling method, including: Step I, determining the rule of filling dummy patterns, in accordance with required DR values and isolation rules of patterns; Step II, finding out blank Fields within said layout that need to be filled with dummy patterns; Step III, by following said rule of filling dummy patterns, filling dummy patterns within blank Fields on layouts. Implementing a Smart Dummy Pattern Filling, which enables the Data Ratio (DR) of dummy patterns to come infinitely close the required DR value after completing the filling of dummy patterns.

Abstract: A dummy pattern filling method, including: Step I, determining the rule of filling dummy patterns, in accordance with required DR values and isolation rules of patterns; Step II, finding out blank Fields within said layout that need to be filled with dummy patterns; Step III, by following said rule of filling dummy patterns, filling dummy patterns within blank Fields on layouts. Implementing a Smart Dummy Pattern Filling, which enables the Data Ratio (DR) of dummy patterns to come infinitely close the required DR value after completing the filling of dummy patterns.

Abstract: A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate.

Abstract: A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate.

Abstract: An Electrically Erasable Programmable Read-Only Memory (EEPROM) and an EEPROM storage array are provided. The EEPROM storage array includes: at least one storage area, wherein the storage area comprises M word lines in a row direction, 8 bit lines in a column direction, 8 source lines in the column direction, and a plurality of storage units arranged in M rows and 8 columns, where M is a positive integer; and wherein gate electrodes of storage units in a same row are connected with a same word line, drain electrodes of storage units in a same column are connected with a same bit line, and source electrodes of storage units in a same column are connected with a same source line. The EEPROM's volume is reduced by connecting source electrodes of storage units in a same column to a same source line, and arranging the source lines in a column direction.

Abstract: A memory includes an array of memory cells including a plurality of memory cells with a common source, wherein each of the plurality of memory cells with a common source includes two sub-memory cells, each of the sub-memory cells corresponds to a bit line, and the respective bits are electrically independent. Each of the sub-memory cells in the memory according to the disclosure corresponds to a bit line, and the respective bit lines are electrically independent, thereby effectively avoiding interference to other memory cells which will not be programmed during a program operation.

Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Abstract: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Abstract: A memory includes: a semiconductor substrate (1), a doped source area (2) and a doped drain area (3) set in the semiconductor substrate (1), and a channel area (4) set between said doped source area (2) and said doped drain area (3); a first insulating layer (5) located on the semiconductor substrate (1), a charge memory layer (6) composed of polysilicon located on said first insulating layer (5); an SiGe conducting layer (7) set in said charge memory layer (6).

Abstract: A capacitor structure in a semiconductor device is provided. The capacitor structure includes a first power rail on a topmost level of the semiconductor device, and a second power rail on the topmost level of the semiconductor device. The capacitor structure also includes a dielectric layer disposed over at least a portion of one of the first power rail and the second power rail. The capacitor structure further includes a conductive layer disposed over and between the first power rail and the second power rail where the conductive layer is in electrical contact with the power rail not having the dielectric layer, and the conductive layer is disposed over the dielectric layer.

Abstract: A capacitor structure in a semiconductor device is provided. The capacitor structure includes a first power rail on a topmost level of the semiconductor device, and a second power rail on the topmost level of the semiconductor device. The capacitor structure also includes a dielectric layer disposed over at least a portion of one of the first power rail and the second power rail. The capacitor structure further includes a conductive layer disposed over and between the first power rail and the second power rail where the conductive layer is in electrical contact with the power rail not having the dielectric layer, and the conductive layer is disposed over the dielectric layer.

Abstract: A dual port memory cell is provided. The dual port memory cell includes a storage cell. A first bitline pair defining access to the storage cell by a first port and a second bitline pair defining access to the storage cell by a second port are defined. Each bitline of the first and second bitline pairs is defined from metallization line features, and the first bitline pair is defined on one side of the storage cell and the second bitline pair is defined on the other side of the storage cell. The bitlines of the first port are physically separate from the bitlines of the second port.

Abstract: A method for fabricating an SRAM device having a standard well tub, where an additional well tub is deposited within the standard well tub. In this manner, the dopant concentration is increased in the well area of the SRAM device, which increases both the isolation punchthrough tolerance and the SER immunity of the device. The additional well tub is deposited to a depth that is shallower than the standard well tub. The additional well tub is deposited using an ion implantation process using the same mask set as that used for the threshold voltage adjustment deposition. Thus, no additional mask layer is required to deposit the additional well tub, and the all of the expenses normally associated with an additional mask layer are avoided.

Abstract: An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0.25 &mgr;m SRAM design having one or more N wells of a conventional depth not exceeding about 0.5 &mgr;m, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 &mgr;m. The deep N well of the 0.25 &mgr;m SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 &mgr;m, and preferably at least about 2 &mgr;m.