Patents by Inventor Wei-Shan Liao
Wei-Shan Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9590039Abstract: A semiconductor structure and a method for forming same are provided. The semiconductor structure includes a bipolar transistor. The bipolar transistor includes a base doped contact, an emitter doped contact, a collector doped contact, and well regions. The base doped contact, the emitter doped contact and the collector doped contact are formed in the different well regions having different dopant conditions from each other.Type: GrantFiled: December 20, 2013Date of Patent: March 7, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventor: Wei-Shan Liao
-
Patent number: 9455319Abstract: A semiconductor device and an operating method of the same are disclosed. The semiconductor device includes a substrate, a source region, a drain region, a gate structure, a first lightly-doped region, and a first isolation region. The source region and the drain region are formed in the substrate. The gate structure is formed on the substrate and between the source region and the drain region. The first lightly-doped region is formed below the source region. The first isolation region is formed in the substrate and surrounding the source region, the drain region, and the first lightly-doped region. The source region and the drain region have a first-polarity, and the first lightly-doped region and the first isolation region have a second-polarity.Type: GrantFiled: May 12, 2014Date of Patent: September 27, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventor: Wei-Shan Liao
-
Patent number: 9202939Abstract: A Schottky diode is disclosed. The Schottky diode includes: a substrate, a first-type buried layer in the substrate, a cathode region, an anode region surrounding the cathode region, and a first-type guard ring surrounding the anode region and connected to the first-type buried layer. The cathode region preferably includes a high-voltage second-type lightly doped drain in the substrate, a first-type well surrounding the high-voltage second-type lightly doped drain, and a first-type doping region in the first-type well and surrounding the high-voltage second-type lightly doped drain.Type: GrantFiled: February 11, 2014Date of Patent: December 1, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventor: Wei-Shan Liao
-
Publication number: 20150325639Abstract: A semiconductor device and an operating method of the same are disclosed. The semiconductor device includes a substrate, a source region, a drain region, a gate structure, a first lightly-doped region, and a first isolation region. The source region and the drain region are formed in the substrate. The gate structure is formed on the substrate and between the source region and the drain region. The first lightly-doped region is formed below the source region. The first isolation region is formed in the substrate and surrounding the source region, the drain region, and the first lightly-doped region. The source region and the drain region have a first-polarity, and the first lightly-doped region and the first isolation region have a second-polarity.Type: ApplicationFiled: May 12, 2014Publication date: November 12, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventor: Wei-Shan Liao
-
Publication number: 20150228808Abstract: A Schottky diode is disclosed. The Schottky diode includes: a substrate, a first-type buried layer in the substrate, a cathode region, an anode region surrounding the cathode region, and a first-type guard ring surrounding the anode region and connected to the first-type buried layer. The cathode region preferably includes a high-voltage second-type lightly doped drain in the substrate, a first-type well surrounding the high-voltage second-type lightly doped drain, and a first-type doping region in the first-type well and surrounding the high-voltage second-type lightly doped drain.Type: ApplicationFiled: February 11, 2014Publication date: August 13, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventor: Wei-Shan Liao
-
Publication number: 20150179779Abstract: A semiconductor structure and a method for forming same are provided. The semiconductor structure includes a bipolar transistor. The bipolar transistor includes a base doped contact, an emitter doped contact, a collector doped contact, and well regions. The base doped contact, the emitter doped contact and the collector doped contact are formed in the different well regions having different dopant conditions from each other.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventor: Wei-Shan Liao
-
Patent number: 8803235Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.Type: GrantFiled: October 3, 2013Date of Patent: August 12, 2014Assignee: United Microelectronics Corp.Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
-
Patent number: 8786362Abstract: A Schottky diode having a current leakage protection structure includes a Schottky diode unit, a first isolation portion and a second isolation portion. The Schottky diode unit is defined in a substrate and includes a metalized anode, an active region having dopants of first conductive type, a cathode and at least one isolation structure. The first isolation portion having dopants of second conductive type is formed between substrate and active region, and the first isolation portion includes a first well disposed beneath active region, and a first guard ring surrounding active region and connecting to the first well. The second isolation portion having dopants of first conductive type is formed between substrate and the first isolation portion, and the second isolation portion includes a second well disposed beneath the first well, and a second guard ring surrounding the first guard ring and connecting to the second well.Type: GrantFiled: June 4, 2013Date of Patent: July 22, 2014Assignee: United Microelectronics CorporationInventors: An-Hung Lin, Wei-Shan Liao, Bo-Jui Huang, Hong-Ze Lin, Ting-Zhou Yan, Wen-Chun Chang
-
Publication number: 20140048877Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.Type: ApplicationFiled: August 14, 2012Publication date: February 20, 2014Inventors: Wei-Shan LIAO, An-Hung LIN, Hong-Ze LIN, Bo-Jui HUANG
-
Publication number: 20140035034Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.Type: ApplicationFiled: October 3, 2013Publication date: February 6, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
-
Patent number: 8643104Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.Type: GrantFiled: August 14, 2012Date of Patent: February 4, 2014Assignee: United Microelectronics Corp.Inventors: Wei-Shan Liao, An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang
-
Patent number: 8587058Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.Type: GrantFiled: January 2, 2012Date of Patent: November 19, 2013Assignee: United Microelectronics Corp.Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen, Ming-Yong Jian
-
Patent number: 8581338Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.Type: GrantFiled: May 12, 2011Date of Patent: November 12, 2013Assignee: United Microelectronics Corp.Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
-
Patent number: 8482063Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.Type: GrantFiled: November 18, 2011Date of Patent: July 9, 2013Assignee: United Microelectronics CorporationInventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Wei-Chun Chang, Chun-Yao Lee, Kun-Yi Chou
-
Publication number: 20130168767Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.Type: ApplicationFiled: January 2, 2012Publication date: July 4, 2013Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen, Ming-Yong Jian
-
Patent number: 8450801Abstract: A lateral-diffusion metal-oxide-semiconductor device includes a semiconductor substrate having at least a field oxide layer, a gate having a layout pattern of a racetrack shape formed on the substrate, a common source formed in the semiconductor substrate and enclosed by the gate, and a drain surrounding the gate and formed in the semiconductor substrate. The gate covers a portion of the field oxide layer. The common source includes a first doped region having a first conductive type and a plurality of islanding second doped regions having a second conductive type. The drain includes a third doped region having the first conductive type. The third doped region overlaps a portion of the field oxide layer and having an overlapping area between the third doped region and the field oxide layer.Type: GrantFiled: August 27, 2010Date of Patent: May 28, 2013Assignee: United Microelectronics Corp.Inventors: Hong-Ze Lin, Bo-Jui Huang, Chin-Lung Chen, Ting-Zhou Yan, Wei-Shan Liao, Han-Min Huang, Chun-Yao Lee, Kun-Yi Chou
-
Publication number: 20130126968Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.Type: ApplicationFiled: November 18, 2011Publication date: May 23, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: An-Hung LIN, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Wei-Chun Chang, Chun-Yao Lee, Kun-Yi Chou
-
Publication number: 20120286359Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.Type: ApplicationFiled: May 12, 2011Publication date: November 15, 2012Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
-
Publication number: 20120049277Abstract: A lateral-diffusion metal-oxide-semiconductor device includes a semiconductor substrate having at least a field oxide layer, a gate having a layout pattern of a racetrack shape formed on the substrate, a common source formed in the semiconductor substrate and enclosed by the gate, and a drain surrounding the gate and formed in the semiconductor substrate. The gate covers a portion of the field oxide layer. The common source includes a first doped region having a first conductive type and a plurality of islanding second doped regions having a second conductive type. The drain includes a third doped region having the first conductive type. The third doped region overlaps a portion of the field oxide layer and having an overlapping area between the third doped region and the field oxide layer.Type: ApplicationFiled: August 27, 2010Publication date: March 1, 2012Inventors: Hong-Ze Lin, Bo-Jui Huang, Chin-Lung Chen, Ting-Zhou Yan, Wei-Shan Liao, Han-Min Huang, Chun-Yao Lee, Kun-Yi Chou