Abstract: A semiconductor system and a method for operating the semiconductor system are provided. The semiconductor system comprises a duty cycle corrector (DCC) and an analog quadrature error corrector (QEC). The DCC is configured to receive an input clock signal to adjust a duty cycle of the input clock signal and generate a first modified clock signal. The analog QEC is configured to receive the first modified clock signal. The analog QEC is configured to adjust a delay of the first modified clock signal and generate a first output clock signal and a second output clock signal. The second output clock signal delays or advances a quarter of period from the first output clock signal. The analog QEC comprises a first inverter chain, a phase error detector (PED) and a first low-pass filter (LPF).

Abstract: A clock synthesizer is provided. A clock buffer is configured to store an input clock signal. A Duty Cycle Corrector (DCC) circuit is connected to the clock buffer. The DCC circuit is configured to receive the input clock signal from the clock buffer, receive a control signal, and adjust a duty cycle of the input clock signal based on the control signal. An output clock signal comprising the duty cycle corrected input clock signal is generated. The output clock signal is provided. A current source is configured to sink a clamping current to the DCC circuit.

Abstract: A device includes a clock signal generator and a transmitter circuit. The clock signal generator receives a first input clock signal, generates an output clock signal, and includes a phase generator and a duty cycle corrector. The phase generator generates a plurality of second input clock signals from the input clock signal. The duty cycle corrector adjusts a duty cycle of the second input clock signal with reference to a control signal, generates a single-ended input signal and complementary output signals from the single-ended input signal, compares the complementary output signals, and generates a result of comparison that serves as the control signal. The transmitter circuit receives an input data signal, processes the input data signal in response to the output clock signal, generates an output data signal, and transmits the output data signal.

Abstract: A circuit may comprise a first multiplexer, a second multiplexer, a combination of logic gates, a third multiplexer, a first low-pas filter, and a second low-pass filter. The first multiplexer can be configured to receive and select a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. Respective phases of the first to fourth clock signals are related to each other. The second multiplexer can be configured to receive and select the first to fourth clock signals. The combination of logic gates may comprise a first logic gate and a second logic gate. The combination of logic gates can be coupled to the second multiplexer and can be configured to receive the second plurality of the first to fourth clock signals. The third multiplexer can be configured to receive and select the first to fourth outputs.

Abstract: A duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. A duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. The DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

Abstract: A semiconductor system and a method for operating the semiconductor system are provided. The semiconductor system comprises a duty cycle corrector (DCC) and an analog quadrature error corrector (QEC). The DCC is configured to receive an input clock signal to adjust a duty cycle of the input clock signal and generate a first modified clock signal. The analog QEC is configured to receive the first modified clock signal. The analog QEC is configured to adjust a delay of the first modified clock signal and generate a first output clock signal and a second output clock signal. The second output clock signal delays or advances a quarter of period from the first output clock signal. The analog QEC comprises a first inverter chain, a phase error detector (PED) and a first low-pass filter (LPF).

Abstract: Circuits, devices, and methods relating to a phase interpolator are described herein. The phase interpolator may comprise a first plurality of functional units and a second plurality of functional units, and may be controlled, in part, by an encoding scheme. The phase interpolator may be designed to have a layout such that a turn-on resistance across the first plurality of functional units in response to a first code of the encoding scheme is equal to a turn-on resistance across the second plurality of functional units in response to a second code of the encoding scheme.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

Abstract: A clock synthesizer is provided. The Clock synthesizer includes a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

Abstract: A clock synthesizer is provided. The Clock synthesizer includes a a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

Abstract: One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

Abstract: A clock synthesizer is provided. A clock buffer is configured to store an input clock signal. A Duty Cycle Corrector (DCC) circuit is connected to the clock buffer. The DCC circuit is configured to receive the input clock signal from the clock buffer, receive a control signal, and adjust a duty cycle of the input clock signal based on the control signal. An output clock signal comprising the duty cycle corrected input clock signal is generated. The output clock signal is provided. A current source is configured to sink a clamping current to the DCC circuit.

Abstract: A clock synthesizer is provided. The Clock synthesizer includes a a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.