Abstract: A light-emitting device includes a semiconductor stack, an insulating reflective structure having an opening, and an electrode located on the insulating reflective structure and filled in the opening to electrically connect to the semiconductor stack. The semiconductor stack having includes a main surface, and a side surface inclined to the main surface. The light-emitting device has a dominant wavelength and a peak wavelength. The insulating reflective structure includes: a first part located on the main surface and having a first thickness; and a second part located on the side surface and having a second thickness different from the first thickness. The second part of the insulating reflective structure has a reflectivity of more than 90% for the dominant wavelength or the peak wavelength within an incident angle of 0° to 30°.

Abstract: A chip-on-board module is provided. The chip-on-board module includes a chip and a substrate. The chip includes a plurality of chip contacts. The substrate includes a plurality of first leads and a plurality of second leads. The first leads and the second leads are coupled to a portion of the chip contacts. The first leads are arranged along a first axis. The second leads are arranged along a second axis. A first axis included angle is formed between the first axis and the second axis, and the first axis included angle is between 100o and 170o.

Abstract: In an embodiment, a method may include forming a multi-layer stack over a substrate. The multi-layer stack has alternating layers of first semiconductor layers and second semiconductor layers. The method may also include removing the first semiconductor layers. Furthermore, the method may include forming a disposable material between the second semiconductor layers. In addition, the method may include performing a first implantation process on the disposable material and the second semiconductor layers. Moreover, the method may include forming source/drain regions adjacent to the second semiconductor layers and the disposable material. The method may also include replacing the disposable material with a metal gate structure.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a nucleation layer, a strain relief layer, a P-doping GaN layer, a GaN channel layer and an AlGaN barrier layer. The strain relief layer is disposed on the nucleation layer. The strain relief layer has a plurality of modulated P-doping concentrations. The P-doping GaN layer is disposed on the strain relief layer. The GaN channel layer is disposed on the P-doping GaN layer. The AlGaN barrier layer is disposed on the GaN channel layer.

Abstract: A chip-on-board module is provided. The chip-on-board module includes a chip and a substrate. The chip includes a plurality of chip contacts. The substrate includes a plurality of first leads and a plurality of second leads. The first leads and the second leads are coupled to a portion of the chip contacts. The first leads are arranged along a first axis. The second leads are arranged along a second axis. A first axis included angle is formed between the first axis and the second axis, and the first axis included angle is between 100° and 170°.

Abstract: An analysis method and an electronic device for a coronary artery image are provided. The method includes: performing segmentation on the coronary artery image based on a machine learning model to obtain a plurality of categories; setting one of the categories as a currently evaluated vessel, and determining whether a pixel quantity corresponding to the currently evaluated vessel is less than a first threshold to generate a result; and determining whether the coronary artery image has an occlusion phenomenon according to the result.

Abstract: The present disclosure provides a method of extracting DNA from fish and a method of using the DNA extract. The DNA extract provided herein produces the efficacies in ameliorating or treating osteoarthritis or osteoporosis. Mice experiments prove that clinical parameters associated with osteoarthritis or osteoporosis are improved by the DNA extract. In addition, the DNA extract exhibits free radical scavenging activities, anti-oxidative activities, anti-depressant activities, and black hair promoting activities.

Abstract: A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; etching back the dummy gate layer; performing an implantation process to the dummy gate layer to form an implantation region in the dummy gate layer, wherein a vertical thickness of the dummy gate layer is greater than a vertical thickness of the implantation region; forming a patterned hard mask stack over the implantation region; patterning the implantation region and the dummy gate layer by using the patterned hard mask stack as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.

Abstract: A method for manufacturing a semiconductor structure includes: forming a channel layer on a substrate; forming a first barrier layer on the channel layer, the first barrier layer being made of a material represented by Alx1Ga1-x1N; forming a doped layer on the first barrier layer; forming a second barrier layer over the first barrier layer opposite to the channel layer, the second barrier layer being made of a material represented by Alx2Ga1-x2N, x2 being greater than x1; and forming a third barrier layer on the second barrier layer opposite to the first barrier layer, the third barrier layer being made of a material represented by Alx3Ga1-x3N, x3 being smaller than x2.

Abstract: A tank wall thickness inspecting module includes a base mount, two guide rails parallel extending from the base mount, a slide slidably connected with the two guide rails, an actuator disposed between the base mount and the slide to drive the slide to move along the two guide rails, a posture-adjustable seat having two guide holes through which the two guide rails extend, a buffer device disposed between the slide and the posture-adjustable seat to enable that the posture-adjustable seat changes a distance and an angle relative to the slide, and a probe disposed with the posture-adjustable seat and provided with a detection surface. The detection surface is flush with or protrudes out of a bottom surface of the posture-adjustable seat. As a result, the angle of the probe can be automatically adjusted based on the surface under inspection.

Abstract: A method includes forming a shallow trench isolation region aside of a protruding fin. The protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure. The method further includes forming a dielectric layer on the shallow trench isolation region, forming a dummy gate stack over the protruding fin, and performing an implantation process to form a protection layer. The protection layer covers the shallow trench isolation region. A sacrificial layer in the protruding fin is removed to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure. A disposable interposer is formed in the space. The dummy gate stack is then removed, followed by performing an etching process to remove the disposable interposer, and forming a replacement gate stack, wherein a portion of the replacement gate stack is filled in the space.

Abstract: A method includes patterning a substrate to form a channel structure over the substrate. An isolation structure is formed over the substrate and adjacent to the channel structure. A dummy layer is deposited to cover the channel structure and the isolation structure. A bottom mask layer is deposited over the dummy layer. An implantation process is performed to the bottom mask layer to relax a stress of the bottom mask layer. A photoresist pattern is formed over the implanted bottom mask layer. The implanted bottom mask layer is patterned through the photoresist pattern. The dummy layer is patterned through the patterned and implanted bottom mask layer to form a dummy gate structure across the channel structure. The dummy gate structure is replaced with a metal gate structure.

Abstract: A low complexity clock drift estimation scheme for UWB-MMS ranging is proposed, assuming sampling frequency offset (SFO) and carrier frequency offset (CFO) are driven from the same clock source. SFO is first estimated with the multiple CIR fragments, and it is used to compensate the CFO for the CIR fragments. Then a fine CFO estimate is obtained from the compensated CIRs. Combining the coarse SFO and fine CFO estimate to resample and phase rotate the original CIRs can significantly improve the performance for CIR combining, thus, improve the performance for ranging.

Abstract: In an embodiment, a method may include forming a multi-layer stack over a substrate. The multi-layer stack has alternating layers of first semiconductor layers and second semiconductor layers. The method may also include removing the first semiconductor layers. Furthermore, the method may include forming a disposable material between the second semiconductor layers. In addition, the method may include performing a first implantation process on the disposable material and the second semiconductor layers. Moreover, the method may include forming source/drain regions adjacent to the second semiconductor layers and the disposable material. The method may also include replacing the disposable material with a metal gate structure.

Abstract: A method includes forming a fin protruding from a semiconductor substrate; forming a dummy gate stack over the fin, wherein forming the dummy gate stack includes depositing a layer of amorphous material over the fin; performing an anneal process on the layer of amorphous material, wherein the anneal process recrystallizes the layer of amorphous material into a layer of polycrystalline material, wherein the anneal process includes heating the layer of amorphous material for less than one millisecond; and patterning the layer of polycrystalline material; forming an epitaxial source/drain region in the fin adjacent the dummy gate stack; and removing the dummy gate stack and replacing the dummy gate stack with a replacement gate stack.

Abstract: In an embodiment, a device includes: a first semiconductor nanostructure; a second semiconductor nanostructure adjacent the first semiconductor nanostructure; a first source/drain region on a first sidewall of the first semiconductor nanostructure; a second source/drain region on a second sidewall of the second semiconductor nanostructure, the second source/drain region completely separated from the first source/drain region; and a source/drain contact between the first source/drain region and the second source/drain region.

Abstract: Improved control of via anchor profiles in metals at a contact layer can be achieved by slowing down an anchor etching process and by introducing a passivation operation. By first passivating a metallic surface, etchants can be prevented from dispersing along grain boundaries, thereby distorting the shape of the via anchor. An iterative scheme that involves multiple cycles of alternating passivation and etching operations can control the formation of optimal via anchor profiles. When a desirable anchor shape is achieved, the anchor maintains structural integrity of the vias, thereby improving reliability of the interconnect structure.

Abstract: A method of manufacturing a High-Electron-Mobility Transistor (HEMT) includes: preparing a substrate; forming a first buffer over the substrate; forming a second buffer over the first buffer, wherein forming the second buffer includes doping a first thickness of a material such as gallium nitride (GaN) with a first concentration of a dopant such as carbon, and doping a second thickness of the material with a second concentration of the dopant such that the second concentration of dopant has a gradient though the second thickness which progressively decreases in a direction away from the first thickness; forming a channel layer such as a GaN channel over the second buffer; forming a barrier layer such as aluminum gallium nitride (AlGaN) over the channel layer; and forming drain, source and gate terminals for the HEMT.

Abstract: A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; depositing a hard mask stack over the dummy gate layer; depositing a photoresist bottom layer over the hard mask stack, wherein the photoresist bottom layer has a first stress; performing an implantation process to the photoresist bottom layer to form an implanted bottom layer with a second stress closer to 0 than the first stress; patterning the implanted bottom layer; patterning the hard mask stack and the dummy gate layer by using the patterned implanted bottom layer as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.

Abstract: Improved control of via anchor profiles in metals at a contact layer can be achieved by slowing down an anchor etching process and by introducing a passivation operation. By first passivating a metallic surface, etchants can be prevented from dispersing along grain boundaries, thereby distorting the shape of the via anchor. An iterative scheme that involves multiple cycles of alternating passivation and etching operations can control the formation of optimal via anchor profiles. When a desirable anchor shape is achieved, the anchor maintains structural integrity of the vias, thereby improving reliability of the interconnect structure.