Patents by Inventor Weiting Jiang

Weiting Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942459
    Abstract: A semiconductor device package includes a first substrate having an electrical circuit, semiconductor dies stacked one on top of the other, and bond wires electrically connected one to another. The bond wires electrically couple the semiconductor dies to one another and to the electrical circuit. There is a first bond wire having a first portion connected to a first semiconductor die, a second portion connected to a second semiconductor die, and an intermediate portion between the first portion and second portion. The semiconductor device package further includes a molding compound encapsulating the semiconductor dies, and the first and second portions of the first bond wire. The intermediate portion of the first bond wire is exposed along a top planar surface of the molding compound. The semiconductor device package may be used for coupling one or more other semiconductor device packages thereto via the exposed intermediate portion.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: March 26, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hua Tan, Hope Chiu, Weiting Jiang, Elley Zhang, Cong Zhang, Simon Dong, Jerry Tang, Rosy Zhao
  • Patent number: 11939578
    Abstract: The present invention relates to the field of biomedicine, particularly to double-stranded RNA molecules targeting CKIP-1 and uses thereof, particularly to use of the double-stranded RNA molecules for the treatment of inflammatory diseases such as arthritis, particularly rheumatoid arthritis.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: March 26, 2024
    Assignee: BEIJING TIDE PHARMACEUTICAL CO., LTD.
    Inventors: Yanping Zhao, Hongjun Wang, Yuanyuan Jiang, Weiting Zhong, Jianmei Pang, Gong Li, Xiang Li, Yixin He, Liying Zhou, Yanan Liu
  • Publication number: 20230411179
    Abstract: The present disclosure generally relates to ensuring a plasma plume or cloud that forms during a laser cutting process does not lead to undesired re-deposition of material onto the substrate. At least one electrode is biased to draw the electrons of the plasma plume or cloud towards the electrode and away from the substrate. A vacuum port and/or a blower may be strategically located to ensure proper gas flow away from the substrate and hence, directing of the electrons away from the substrate. In so doing, material re-deposition is less likely to occur.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cong ZHANG, Hope CHIU, Yiqin HUANG, Guocheng ZHONG, Weiting JIANG, Dongpeng XUE
  • Publication number: 20230377972
    Abstract: A die separation ring that causes non-uniform expansion of a semiconductor wafer during a semiconductor wafer expansion process. The die separation ring includes an annular body that extends about a central axis. The annular body of the die separation ring includes a first portion having a first elevation and a second portion having a second elevation that is lower than the first elevation. A third portion extends between the first portion and the second portion forming a transition between the first portion and the second portion.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Inventors: Shuo Li, Jacky Liu, Lance Liu, Legend Xin, Weiting Jiang, Zhenghao Wu, Bo Yang
  • Publication number: 20230260975
    Abstract: A semiconductor device package includes a first substrate having an electrical circuit, semiconductor dies stacked one on top of the other, and bond wires electrically connected one to another. The bond wires electrically couple the semiconductor dies to one another and to the electrical circuit. There is a first bond wire having a first portion connected to a first semiconductor die, a second portion connected to a second semiconductor die, and an intermediate portion between the first portion and second portion. The semiconductor device package further includes a molding compound encapsulating the semiconductor dies, and the first and second portions of the first bond wire. The intermediate portion of the first bond wire is exposed along a top planar surface of the molding compound. The semiconductor device package may be used for coupling one or more other semiconductor device packages thereto via the exposed intermediate portion.
    Type: Application
    Filed: February 14, 2022
    Publication date: August 17, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Hua Tan, Hope Chiu, Weiting Jiang, Elley Zhang, Cong Zhang, Simon Dong, Jerry Tang, Rosy Zhao
  • Publication number: 20230129628
    Abstract: A semiconductor device package includes a multi-layer substrate including a bottom layer and a top layer. One or more dies are mounted on and electrically coupled to the top layer of the substrate. An electromagnetic interference (EMI) shield encapsulates the substrate and the semiconductor dies. A first plurality of conductive stubs is positioned around edges of the top layer of the substrate. Each of the conductive stubs includes an edge portion having a first thickness and in contact with the EMI shield. A second plurality of conductive stubs is positioned around edges of the bottom layer of the substrate. Each of the second plurality of conductive stubs includes an edge portion having a second thickness less than the first thickness and in contact with the EMI shield.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 27, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Simon Dong, Hope Chiu, Weiting Jiang, Elley Zhang, Kent Yang, Hua Tan, Jerry Tang, Rui Guo
  • Publication number: 20230102959
    Abstract: A semiconductor package includes a substrate having a top planar surface and a semiconductor die mounted on the top planar surface of the substrate. Bond wires electrically connect the semiconductor die to the substrate. Flow control dams are integrally formed with the top planar surface of the substrate and each flow control dam protrudes from the top planar surface of the substrate at a location proximate to the bond wires. The flow control dams reduce the occurrence of wire sweep in the bond wires electrically connected to the substrate and semiconductor die.
    Type: Application
    Filed: September 30, 2021
    Publication date: March 30, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Hope Chiu, Hua Tan, Kent Yang, Weiting Jiang, Jerry Tang, Simon Dong, Yuequan Shi, Rosy Zhao
  • Patent number: 10607955
    Abstract: A device may include a fan-out structure that has a plurality of integrated circuits. The integrated circuits may be of different types, such as by being configured differently or configured to perform different functions. The fan-out structure may be coupled to another integrated circuit structure, such as a die stack. For example, the fan-out structure may be coupled to a top surface or a bottom surface of the integrated circuit structure, or may otherwise be disposed within a vertical profile defined by the integrated circuit structure. Horizontally-extending and vertically-extending paths may be disposed in between and around the combined fan-out structure and integrated circuit structure to enable the integrated circuits of the two structures to communicate.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 31, 2020
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Chin-Tien Chiu, Chih-Chin Liao, Weiting Jiang, Hem Takiar
  • Publication number: 20180366429
    Abstract: A device may include a fan-out structure that has a plurality of integrated circuits. The integrated circuits may be of different types, such as by being configured differently or configured to perform different functions. The fan-out structure may be coupled to another integrated circuit structure, such as a die stack. For example, the fan-out structure may be coupled to a top surface or a bottom surface of the integrated circuit structure, or may otherwise be disposed within a vertical profile defined by the integrated circuit structure. Horizontally-extending and vertically-extending paths may be disposed in between and around the combined fan-out structure and integrated circuit structure to enable the integrated circuits of the two structures to communicate.
    Type: Application
    Filed: June 28, 2017
    Publication date: December 20, 2018
    Applicant: SunDisk Semiconductro (Shanghai) Co. Ltd.
    Inventors: Chin-Tien Chiu, Chih-Chin Liao, Weiting Jiang, Hem Takiar
  • Publication number: 20160086827
    Abstract: A memory device including graphical content and a method of making the memory device with graphical content are disclosed. The graphical content is formed on a release media. The release media and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the graphical content is transferred from the release media to the encapsulated memory device.
    Type: Application
    Filed: December 4, 2015
    Publication date: March 24, 2016
    Inventors: Peng Fu, Zhong Lu, Chin Tien Chiu, Cheeman Yu, Matthew Chen, Weiting Jiang
  • Publication number: 20140346686
    Abstract: A memory device including graphical content and a method of making the memory device with graphical content are disclosed. The graphical content is formed on a release media. The release media and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the graphical content is transferred from the release media to the encapsulated memory device.
    Type: Application
    Filed: September 2, 2011
    Publication date: November 27, 2014
    Inventors: Fu Peng, Zhong Lu, Chin Tien Chiu, Cheeman Yu, Matthew Chen, Weiting Jiang