Patents by Inventor Wei-Ting Wang
Wei-Ting Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12238945Abstract: Disclosed is a passivated perovskite structure containing a perovskite layer; and a hindered urea bond-based Lewis acid-base containing layer adjacent the perovskite layer. Also disclosed are solar cells containing the passivated perovskite structure.Type: GrantFiled: January 27, 2022Date of Patent: February 25, 2025Assignee: THE UNIVERSITY OF HONG KONGInventors: Shien Ping Feng, Wei Ting Wang
-
Publication number: 20240099037Abstract: Disclosed is a passivated perovskite structure containing a perovskite layer; and a hindered urea bond-based Lewis acid-base containing layer adjacent the perovskite layer. Also disclosed are solar cells containing the passivated perovskite structure.Type: ApplicationFiled: January 27, 2022Publication date: March 21, 2024Inventors: Shien Ping Feng, Wei Ting Wang
-
Publication number: 20240055479Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a fin structure protruding from a substrate, wherein the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method includes forming a dummy gate structure across the fin structure. The method includes forming a gate spacer on the sidewall of the dummy gate structure. The method includes removing the dummy gate structure to expose the fin structure. The method includes partially removing the second semiconductor material layers to form concave portions on sidewalls of the second semiconductor material layers. The method includes forming dielectric spacers in the concave portions. The method includes removing the first semiconductor material layers to form gaps. The method includes forming a gate structure in the gaps to wrap around the second semiconductor material layers and the dielectric spacers.Type: ApplicationFiled: August 12, 2022Publication date: February 15, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi-Ning JU, Yi-Ruei JHAN, Wei-Ting WANG, Chih-Hao WANG
-
Publication number: 20230420532Abstract: A method of manufacturing an integrated circuit device is provided. The method includes forming a semiconductor fin over a semiconductor substrate; forming an isolation structure surrounding the semiconductor fin; etching a trench in the semiconductor fin; forming a dielectric fin in the trench; after forming the dielectric fin, recessing a top surface of the isolation structure, such that the dielectric fin and the semiconductor fin protrude from the recessed top surface of the isolation structure; and forming a first metal gate structure and a second metal gate structure over the dielectric fin and the semiconductor fin, respectively.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Ruei JHAN, Kuan-Ting PAN, Wei Ting WANG, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
-
Patent number: 11830589Abstract: The disclosure provides a disease classification method and a disease classification device. The disease classification method includes: inputting samples into a first stage model and obtaining a first stage determination result; inputting first samples determined positive by the first stage model into a second stage high specificity model to obtain second samples determined to be positive and third samples determined to be negative and rule in the second samples; inputting fourth samples determined negative by the first stage model into a second stage high sensitivity model to obtain fifth samples determined to be positive and sixth samples determined to be negative and rule out the sixth samples; obtaining a second stage determination result of the second and sixth samples; and inputting the third and fifth samples not ruled in or ruled out into a third stage model and obtaining a third stage determination result of the third and fifth samples.Type: GrantFiled: October 29, 2020Date of Patent: November 28, 2023Assignees: Acer Incorporated, Acer Medical Inc., Taipei Veterans General HospitalInventors: Jun-Hong Chen, Tsung-Hsien Tsai, Chun-Hsien Li, Wei-Ting Wang, Yin-Hao Lee, Hao-Min Cheng
-
Publication number: 20230378881Abstract: The present application provides a control device, a power-supply device, and a method for controlling a power-supply device. The control device, applied to a power converter, includes a primary controller, a secondary controller and a voltage detector, wherein the power converter includes a transformer having a primary winding and a secondary winding. The primary controller is configured to generate a PWM signal having an off-time and an on-time, wherein the power converter is operative to deliver power from the primary winding to the secondary winding during the on-time. The secondary controller monitors an output voltage of the power converter and applies a preset voltage to the secondary winding according to a threshold voltage and the output voltage. The voltage detector, coupled to the primary winding, drives the primary controller to adjust a period of the PWM signal in response to the application of the preset voltage.Type: ApplicationFiled: May 18, 2022Publication date: November 23, 2023Inventors: WEI-TING WANG, YUEH-PING YU
-
Publication number: 20230369327Abstract: In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers is formed, an isolation insulating layer is formed so that the stacked layer are exposed from the isolation insulating layer, a sacrificial cladding layer is formed over at least sidewalls of the exposed stacked layer, a sacrificial gate electrode is formed over the exposed stacked layer, an interlayer dielectric layer is formed, the sacrificial gate electrode is partially recessed to leave a pillar of the remaining sacrificial gate electrode, the sacrificial cladding layer and the first semiconductor layers are removed, a gate dielectric layer wrapping around the second semiconductor layer and a gate electrode over the gate dielectric layer are formed, the pillar is removed, and one or more dielectric layers are formed in a gate space from which the pillar is removed.Type: ApplicationFiled: July 12, 2022Publication date: November 16, 2023Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi Ning JU, Yi-Ruei JHAN, Wei Ting WANG, Chih-Hao WANG
-
Publication number: 20230103750Abstract: A method of balancing workloads among processing elements (PEs) in a neural network processor can include receiving first weights and second weights of a neural network. The first and second weights are associated with a first and a second output channel (OC), respectively. A first PE computes a partial sum (PSUM) of an output activation of the first OC based on the non-zero weights in the first weights. A second PE computes a PSUM of an output activation of the second OC based on the non-zero weights in the second weights. A controller can allocate one or more non-zero weights of the first weights to the second PE for computing the PSUM of the output activation of the first OC to balance a workload.Type: ApplicationFiled: October 6, 2021Publication date: April 6, 2023Applicant: MEDIATEK INC.Inventors: Wei-Ting WANG, Jeng-Yun HSU, Shao-Yu WANG, Han-Lin LI
-
Patent number: 11578417Abstract: A nano-twinned crystal film and a method thereof are disclosed. The method of fabricating a nano-twinned crystal film includes utilizing an electrolyte solution including copper salt, acid, and a water or alcohol-soluble organic additive, and performing electrodeposition, under conditions of a current density of 20˜100 mA/cm2, a voltage of 0.2˜1.0V, and a cathode-anode distance of 10˜300 mm, to form the nano-twinned crystal film on a surface at the cathode. The nano-twinned crystal film formed by the method includes a plurality of nano-twinned copper grains and a region of random crystal phases between some of adjacent nano-twinned copper grains, wherein at least some of the nano-twinned copper grains have a pillar cap configuration with a wide top and a narrow bottom.Type: GrantFiled: December 28, 2020Date of Patent: February 14, 2023Assignee: DOCTECH LIMITEDInventors: Wei-Ting Wang, Shien-Ping Feng, Yu-Ting Huang, Sheng-Jye Cherng, Chih-Chun Chung
-
Patent number: 11529083Abstract: A physiological status evaluation method and a physiological status evaluation apparatus are provided. The method includes the following: obtaining original electrocardiogram data of a user by an electrocardiogram detection apparatus; converting the original electrocardiogram data into digital integration data; obtaining a plurality of physiological characteristic parameters according to the digital integration data; filtering the physiological characteristic parameters for at least one notable characteristic parameter through at least one filter model, where decision importance of the at least one notable characteristic parameter in a decision process of the at least one filter model is greater than a threshold; building a prediction model according to the at least one notable characteristic parameter; and evaluating a physiological status of the user through the prediction model.Type: GrantFiled: October 29, 2020Date of Patent: December 20, 2022Assignees: Acer Incorporated, Taipei Veterans General Hospital, Acer Medical Inc.Inventors: Chun-Hsien Li, Tsung-Hsien Tsai, Jun-Hong Chen, Wei-Ting Wang, Yin-Hao Lee, Hao-Min Cheng
-
Publication number: 20220079463Abstract: A physiological status evaluation method and a physiological status evaluation apparatus are provided. The method includes the following: obtaining original electrocardiogram data of a user by an electrocardiogram detection apparatus; converting the original electrocardiogram data into digital integration data; obtaining a plurality of physiological characteristic parameters according to the digital integration data; filtering the physiological characteristic parameters for at least one notable characteristic parameter through at least one filter model, where decision importance of the at least one notable characteristic parameter in a decision process of the at least one filter model is greater than a threshold; building a prediction model according to the at least one notable characteristic parameter; and evaluating a physiological status of the user through the prediction model.Type: ApplicationFiled: October 29, 2020Publication date: March 17, 2022Applicants: Acer Incorporated, Taipei Veterans General Hospital, Acer Healthcare Inc.Inventors: Chun-Hsien Li, Tsung-Hsien Tsai, Jun-Hong Chen, Wei-Ting Wang, Yin-Hao Lee, Hao-Min Cheng
-
Publication number: 20220084635Abstract: The disclosure provides a disease classification method and a disease classification device. The disease classification method includes: inputting samples into a first stage model and obtaining a first stage determination result; inputting first samples determined positive by the first stage model into a second stage high specificity model to obtain second samples determined to be positive and third samples determined to be negative and rule in the second samples; inputting fourth samples determined negative by the first stage model into a second stage high sensitivity model to obtain fifth samples determined to be positive and sixth samples determined to be negative and rule out the sixth samples; obtaining a second stage determination result of the second and sixth samples; and inputting the third and fifth samples not ruled in or ruled out into a third stage model and obtaining a third stage determination result of the third and fifth samples.Type: ApplicationFiled: October 29, 2020Publication date: March 17, 2022Applicants: Acer Incorporated, Acer Healthcare Inc., Taipei Veterans General HospitalInventors: Jun-Hong Chen, Tsung-Hsien Tsai, Chun-Hsien Li, Wei-Ting Wang, Yin-Hao Lee, Hao-Min Cheng
-
Publication number: 20210198799Abstract: A nano-twinned crystal film and a method thereof are disclosed. The method of fabricating a nano-twinned crystal film includes utilizing an electrolyte solution including copper salt, acid, and a water or alcohol-soluble organic additive, and performing electrodeposition, under conditions of a current density of 20˜100 mA/cm2, a voltage of 0.2˜1.0V, and a cathode-anode distance of 10˜300 mm, to form the nano-twinned crystal film on a surface at the cathode. The nano-twinned crystal film formed by the method includes a plurality of nano-twinned copper grains and a region of random crystal phases between some of adjacent nano-twinned copper grains, wherein at least some of the nano-twinned copper grains have a pillar cap configuration with a wide top and a narrow bottom.Type: ApplicationFiled: December 28, 2020Publication date: July 1, 2021Applicant: Doctech limitedInventors: Wei-Ting WANG, Shien-Ping FENG, Yu-Ting HUANG, Sheng-Jye CHERNG, Chih-Chun CHUNG
-
Patent number: 10942067Abstract: The surface temperature of a portable device is estimated. The portable device includes a sensor for detecting the internal temperature of the portable device. The portable device also includes circuitry for estimating the surface temperature, using the internal temperature and an ambient temperature of the portable device as input to a circuit model. The circuit model describes thermal behaviors of the portable device. The circuitry is operative to identify a scenario in which the portable device operates, and determine the ambient temperature using the scenario and at least the internal temperature.Type: GrantFiled: July 3, 2020Date of Patent: March 9, 2021Assignee: MediaTek Inc.Inventors: Chi-Wen Pan, Pei-Yu Huang, Sheng-Liang Kuo, Jih-Ming Hsu, Tai-Yu Chen, Yun-Ching Li, Wei-Ting Wang
-
Publication number: 20200333193Abstract: The surface temperature of a portable device is estimated. The portable device includes a sensor for detecting the internal temperature of the portable device. The portable device also includes circuitry for estimating the surface temperature, using the internal temperature and an ambient temperature of the portable device as input to a circuit model. The circuit model describes thermal behaviors of the portable device. The circuitry is operative to identify a scenario in which the portable device operates, and determine the ambient temperature using the scenario and at least the internal temperature.Type: ApplicationFiled: July 3, 2020Publication date: October 22, 2020Inventors: Chi-Wen Pan, Pei-Yu Huang, Sheng-Liang Kuo, Jih-Ming Hsu, Tai-Yu Chen, Yun-Ching Li, Wei-Ting Wang
-
Patent number: 10739206Abstract: The surface temperature of a portable device is estimated. A sensor detects the internal temperature of the portable device. The internal temperature and an ambient temperature are used as input to a circuit model that describes thermal behaviors of the portable device. Dynamic thermal management may be performed based on the estimated surface temperature.Type: GrantFiled: December 30, 2017Date of Patent: August 11, 2020Assignee: MediaTek Inc.Inventors: Chi-Wen Pan, Pei-Yu Huang, Sheng-Liang Kuo, Jih-Ming Hsu, Tai-Yu Chen, Yun-Ching Li, Wei-Ting Wang
-
Publication number: 20190303757Abstract: A deep learning accelerator (DLA) includes processing elements (PEs) grouped into PE groups to perform convolutional neural network (CNN) computations, by applying multi-dimensional weights on an input activation to produce an output activation. The DLA also includes a dispatcher which dispatches input data in the input activation and non-zero weights in the multi-dimensional weights to the processing elements according to a control mask. The DLA also includes a buffer memory which stores the control mask which specifies positions of zero weights in the multi-dimensional weights. The PE groups generate output data of respective output channels in the output activation, and share a same control mask specifying same positions of the zero weights.Type: ApplicationFiled: December 14, 2018Publication date: October 3, 2019Inventors: Wei-Ting Wang, Han-Lin Li, Chih Chung Cheng, Shao-Yu Wang
-
Patent number: 10425615Abstract: An image processing apparatus including first circuitry, second circuitry, third circuitry, and fourth circuitry is provided. The first circuitry determines a frame miss rate according to a current frame rate and a target frame rate of an image signal. The second circuitry decreases the target frame rate to the current frame rate when the frame miss rate is greater than a first threshold. The third circuitry increases the target frame rate to an upper-limit frame rate which is determined according to the frame rendering time or memory bandwidth capability, when the frame miss rate is less than a second threshold which is smaller than the first threshold. The fourth circuitry applies the decreased or increased target frame rate for an image to be displayed.Type: GrantFiled: November 8, 2017Date of Patent: September 24, 2019Assignee: MEDIATEK INC.Inventors: Wei-Ting Wang, Han-Lin Li, Yu-Jen Chen, Yu-Ming Lin
-
Patent number: 10156881Abstract: A method for controlling a user experience with an application on an electronic device is provided. The method includes the following steps: detecting a temperature of the electronic device; detecting a power of the electronic device; calculating a power-thermal hint according to the detected temperature and the detected power; and adjusting a complexity level of the application according to at least the power-thermal hint so as to control the user experience with the application.Type: GrantFiled: November 21, 2016Date of Patent: December 18, 2018Assignee: MEDIATEK INC.Inventors: Wei-Ting Wang, Yingshiuan Pan, Lu-Chia Tseng, Yu-Chia Chang
-
Publication number: 20180332252Abstract: An image processing apparatus including first circuitry, second circuitry, third circuitry, and fourth circuitry is provided. The first circuitry determines a frame miss rate according to a current frame rate and a target frame rate of an image signal. The second circuitry decreases the target frame rate to the current frame rate when the frame miss rate is greater than a first threshold. The third circuitry increases the target frame rate to an upper-limit frame rate which is determined according to the frame rendering time or memory bandwidth capability, when the frame miss rate is less than a second threshold which is smaller than the first threshold. The fourth circuitry applies the decreased or increased target frame rate for an image to be displayed.Type: ApplicationFiled: November 8, 2017Publication date: November 15, 2018Inventors: Wei-Ting WANG, Han-Lin LI, Yu-Jen CHEN, Yu-Ming LIN