Abstract: The implementation of the present disclosure discloses a memory and its operation method, a memory system and an electronic device. The memory includes: a memory cell array and a page buffer, the page buffer is disposed corresponding to a bit line of the memory cell array, and the page buffer includes: a precharge and discharge circuit coupled to the bit line through a sense node of the page buffer and including a first type transistor; a plurality of latches respectively coupled to the sense node, wherein at least one of the plurality of latches includes a second type transistor, and a characteristic size of the second type transistor is smaller than that of the first type transistor.

Abstract: According to some aspects, a memory includes a bit line discharge circuit and a bit line coupled to the bit line discharge circuit. The bit line discharge circuit includes a transistor, a control branch, and a first discharge branch. A gate of the transistor is connected with the control branch. One of a source or a drain of the transistor is connected with the first discharge branch. Another of the source or the drain of the transistor is connected with the bit line. The control branch is configured to turn on the transistor. The first discharge branch is configured to discharge the bit line at a set discharge speed when the transistor is turned on.

Abstract: The implementation of the present disclosure discloses a memory and its operation method, a memory system and an electronic device. The memory includes: a memory cell array and a page buffer, the page buffer is disposed corresponding to a bit line of the memory cell array, and the page buffer includes: a precharge and discharge circuit coupled to the bit line through a sense node of the page buffer and including a first type transistor; a plurality of latches respectively coupled to the sense node, wherein at least one of the plurality of latches includes a second type transistor, and a characteristic size of the second type transistor is smaller than that of the first type transistor.

Abstract: The present disclosure discloses a memory device, comprising a plurality of memory blocks each comprising a plurality of memory strings connected between a common source line and a plurality of bit lines and a peripheral circuit, the peripheral circuit comprises a plurality of drive transistors, each drive transistor connected between the common source line and a corresponding bit line of the plurality of bit lines; a first switch circuit connected between a first node and control terminals of the plurality of drive transistors; and a second switch circuit connected between the first node and the common source line.

Abstract: A method of operating a memory device is disclosed. The memory device includes a memory string coupled with a bit line and a common source line. An erase voltage is applied to the bit line and the common source line in an erase operation. The bit line and the common source line are discharged in a discharge operation after the erase operation. A voltage difference between the bit line and the common source line is less than a first predetermined value during a period of the discharge operation.

Abstract: Examples of the present disclosure provide a level shifter, a memory, a memory system, and an electronic apparatus. The level shifter includes: an input circuit, a shifter and an output circuit that are coupled sequentially, wherein the input circuit is configured to generate a first input signal in response to a first level signal; and a regulation circuit coupled to the input circuit and the shifter separately, wherein the regulation circuit is configured to regulate a first control signal output by the shifter in response to the first input signal, wherein a voltage domain of the shifter is different from a voltage domain of the input circuit; and the output circuit is configured to output a second level signal in response to the regulated first control signal, wherein a voltage level of the second level signal is higher than a voltage level of the first level signal.

Abstract: Examples of the present disclosure provide memories, operation methods thereof, and memory systems. A first discharge circuit in an example memory is able to discharge a bit line through a first discharge transistor based on a first voltage received. A second discharge circuit is able to discharge a source line through a second discharge transistor based on a second voltage received. The second voltage is higher than the first voltage, and a discharge current outputted by the second discharge transistor is greater than a discharge current outputted by the first discharge transistor.

Abstract: The present disclosure discloses a memory device, a memory system, and a method for operating a memory device, belonging to the field of storage technology. In the present disclosure, by turning off the first switch circuit, turning on the second switch circuit and providing the first voltage to the first node, the first voltage is applied on the second terminal of the drive transistor through the second switch circuit and the source line, the second terminal of the drive transistor is coupled to a control terminal, such that the voltage of the control terminal changes as the voltage of the second terminal changes, since the first voltage is greater than the threshold voltage of the drive transistor, the drive transistor is turned on to trigger the drive transistor to assist the corresponding memory string in performing a gate-induced-drain-leakage (GIDL) erase.

Abstract: The present disclosure provides a memory device and an operation method thereof, and a memory system, wherein the memory device includes a memory array and a page buffer circuit coupled with a bit line in the memory array; the page buffer circuit includes a first charge circuit and a second charge circuit coupled to a first sensing node along with the first charge circuit; and the operation method of the memory device includes: in a first charge stage, charging the first sensing node to a first voltage through the first charge circuit; and in a second charge stage, charging the first sensing node and the bit line to a second voltage through the second charge circuit, wherein the second voltage is higher than the first voltage.

Abstract: Examples of the present application relate to the field of semiconductors, and disclose a page buffer and an operation method thereof, a memory device and a memory system. The page buffer includes latch circuits, wherein the latch circuits includes: a latch control configuration circuit connected with a first data node and a second data node, and configure the first data node and the second data node to different logic levels respectively in response to a configuration signal, wherein a logic level of the first data node is opposite to a logic level of the second data node; and a latch transmission circuit connected with the first data node, the second data node, and a sense node, and configured to: couple the second data node with the sense node in response to a transmission signal, to transmit a configuration result of the latch control configuration circuit to the sense node.

Abstract: Examples of the present application disclose a page buffer including a plurality of latch circuits. Each latch circuit includes a resetting control circuit, a setting control circuit, a data transmission circuit, and a latch transmission circuit. The resetting control circuit is coupled to a first data node and configured to receive a first supply voltage, so as to determine a potential of the first data node. The setting control circuit is coupled to a second data node and configured to receive the first supply voltage, so as to determine a potential of the second data node. The data transmission circuit is coupled to the first data node and the second data node and configured to receive a second supply voltage. The latch transmission circuit is coupled to the first data node, the second data node, and a sense node. The first supply voltage is higher than the second supply voltage.

Abstract: The present disclosure discloses a memory device, a memory system, and a method for operating a memory device, belonging to the field of storage technology. In the present disclosure, by turning off the first switch circuit, turning on the second switch circuit and providing the first voltage to the first node, the first voltage is applied on the second terminal of the drive transistor through the second switch circuit and the source line, the second terminal of the drive transistor is coupled to a control terminal, such that the voltage of the control terminal changes as the voltage of the second terminal changes, since the first voltage is greater than the threshold voltage of the drive transistor, the drive transistor is turned on to trigger the drive transistor to assist the corresponding memory string in performing a gate-induced-drain-leakage (GIDL) erase.

Abstract: A wand includes a hinge configured to pivotally connect first and second wand segments in an extended configuration and a storage configuration. A first locking mechanism locks the wand in extended configuration. A second locking mechanism includes a rod, a sliding lever, a plunger, and a plunger cavity. The plunger is configured to be received in the plunger cavity to lock the wand in the storage configuration. When in the extended configuration, depressing a single actuator pivots the locking arm, causes the hook/pawl to be removed from the locking cavity, and unlocks the wand. When in the storage configuration, depressing the single actuator causes the rod to move in a first direction, causes the sliding rod to move a second direction, and urges the plunger out of the plunger cavity.

Abstract: The implementation of the present disclosure discloses a memory and its operation method, a memory system and an electronic device. The memory includes: a memory cell array and a page buffer, the page buffer is disposed corresponding to a bit line of the memory cell array, and the page buffer includes: a precharge and discharge circuit coupled to the bit line through a sense node of the page buffer and including a first type transistor; a plurality of latches respectively coupled to the sense node, wherein at least one of the plurality of latches includes a second type transistor, and a characteristic size of the second type transistor is smaller than that of the first type transistor.

Abstract: Examples of the present disclosure disclose a memory and an operation method thereof, a memory system and an electronic device. The memory includes a memory cell array and a page buffer, wherein the page buffer is disposed correspondingly to a bit line of the memory cell array and includes: latches which are coupled to the bit line through a sense node of the page buffer; and at least one common data transmission circuit, wherein a first port of the common data transmission circuit is coupled with the sense node and a second port of the common data transmission circuit is coupled with at least two of the latches, wherein the at least two of the latches are configured for data sensing through the common data transmission circuit respectively.

Abstract: According to some aspects, a memory includes a bit line discharge circuit and a bit line coupled to the bit line discharge circuit. The bit line discharge circuit includes a transistor, a control branch, and a first discharge branch. A gate of the transistor is connected with the control branch. One of a source or a drain of the transistor is connected with the first discharge branch. Another of the source or the drain of the transistor is connected with the bit line. The control branch is configured to turn on the transistor. The first discharge branch is configured to discharge the bit line at a set discharge speed when the transistor is turned on.

Abstract: A method of operating a memory device is disclosed. The memory device includes a memory string coupled with a bit line and a common source line. An erase voltage is applied to the bit line and the common source line in an erase operation. The bit line and the common source line are discharged in a discharge operation after the erase operation. A voltage difference between the bit line and the common source line is less than a first predetermined value during a period of the discharge operation.

Abstract: A wand includes a hinge configured to pivotally connect first and second wand segments in an extended configuration and a storage configuration. A first locking mechanism locks the wand in extended configuration. A second locking mechanism includes a rod, a sliding lever, a plunger, and a plunger cavity. The plunger is configured to be received in the plunger cavity to lock the wand in the storage configuration. When in the extended configuration, depressing a single actuator pivots the locking arm, causes the hook/pawl to be removed from the locking cavity, and unlocks the wand. When in the storage configuration, depressing the single actuator causes the rod to move in a first direction, causes the sliding rod to move a second direction, and urges the plunger out of the plunger cavity.

Abstract: The present disclosure provides a method for discharging a memory device after an erase operation. The method comprises grounding a source line of the memory device; and switching on a discharge transistor to connect a bit line of the memory device to the source line by maintaining a constant voltage difference between a gate terminal of the discharge transistor and the source line. The method also includes comparing an electrical potential of the source line with a first predetermined value; and floating the gate terminal of the discharge transistor when the electrical potential of the source line is lower than the first predetermined value.

Abstract: The present disclosure relates to a method for efficiently enriching lutein in broccoli sprouts under ?-aminobutyric acid combined with sodium chloride stress. In the present disclosure, Qingfeng broccoli seeds with plump particles, uniform size and germination ability are selected as raw materials; after removing impurities and being disinfected by a NaClO solution, the seeds are sprayed with distilled water for one day, then sprayed with a mixed aqueous solution of NaCl and ?-aminobutyric acid, to obtain broccoli sprouts.