Patents by Inventor Weiwei Mao

Weiwei Mao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230091250
    Abstract: The present invention discloses the crystal forms as a JAK inhibitor and their application in the preparation of drugs for the treatment of JAK1 or/and TYK2 related diseases.
    Type: Application
    Filed: February 22, 2021
    Publication date: March 23, 2023
    Inventors: Weiwei MAO, Wenyuan QIAN, Changqing WEI, Liang FANG, Liwei MU, Shuhui CHEN
  • Publication number: 20230017539
    Abstract: Disclosed are a tri-heterocyclic compound as a JAK inhibitor, and the use thereof in the preparation of a drug for treating JAK1- or/and JAK2-related diseases. Specifically, the present invention relates to a compound as shown in formula (I?) or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: November 27, 2020
    Publication date: January 19, 2023
    Inventors: Weiwei MAO, Wenlong LI, Changqing WEI, Wenyuan QIAN, Guoping HU, Jian LI, Shuhui CHEN
  • Patent number: 11427581
    Abstract: Disclosed in the present application are a class of compounds as JAK inhibitors and use thereof in the preparation of medicaments for treating JAK and TYK2 related diseases. Specifically, a compound represented by formula (I), an isomer thereof or a pharmaceutically acceptable salt thereof is disclosed.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: August 30, 2022
    Assignee: ZHUHAI UNITED LABORATORIES CO., LTD.
    Inventors: Weiwei Mao, Hao Wu, Xuejian Zheng, Guoping Hu, Changqing Wei, Jian Li, Shuhui Chen
  • Publication number: 20210155621
    Abstract: Disclosed are a [1,2,4]triazolo[1,5-a]pyridine compound as JAK inhibitor and an application thereof in preparing a drug for treating a disease related to JAK or/and TYK2. Specifically, the present invention relates to a compound represented by formula (I), or an isomer or pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: August 23, 2019
    Publication date: May 27, 2021
    Applicant: Zhuhai United Laboratories Co., Ltd.
    Inventors: Weiwei MAO, Wenyuan QIAN, Xuejian ZHENG, Guoping HU, Changqing WEI, Jian LI, Shuhui CHEN
  • Publication number: 20210070754
    Abstract: Disclosed in the present application are a class of compounds as JAK inhibitors and use thereof in the preparation of medicaments for treating JAK and TYK2 related diseases. Specifically, a compound represented by formula (I), an isomer thereof or a pharmaceutically acceptable salt thereof is disclosed.
    Type: Application
    Filed: January 31, 2019
    Publication date: March 11, 2021
    Inventors: Weiwei MAO, Hao WU, Xuejian ZHENG, Guoping HU, Changqing WEI, Jian LI, Shuhui CHEN
  • Patent number: 10774094
    Abstract: The present invention discloses crystal forms and salt forms of a 7H-pyrrolo[2,3-d]pyrimidine compounds and preparation methods thereof, and further discloses use of the crystal forms and the salt forms in the manufacture of a medicament for treating arthritis.
    Type: Grant
    Filed: November 23, 2017
    Date of Patent: September 15, 2020
    Assignee: Wuxi Fortune Pharmaceutical Co., Ltd
    Inventors: Weiwei Mao, Hao Wu, Qiang Guo, Xuejian Zheng, Yonggang Liao
  • Patent number: 10617690
    Abstract: The present invention discloses a series of JAK inhibitors, and particularly discloses a compound of formula (I) or a pharmaceutically acceptable salt thereof and the use thereof in preparation of drugs for treating diseases related to JAK.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: April 14, 2020
    Assignee: WUXI FORTUNE PHARMACEUTICAL CO., LTD
    Inventors: Hao Wu, Weiwei Mao, Lili Fan, Charles Z. Ding, Shuhui Chen, Fei Wang, Guoping Hu, Jian Li
  • Publication number: 20190218231
    Abstract: The present invention discloses crystal forms and salt forms of a 7H-pyrrolo[2,3-d]pyrimidine compounds and preparation methods thereof, and further discloses use of the crystal forms and the salt forms in the manufacture of a medicament for treating arthritis.
    Type: Application
    Filed: November 23, 2017
    Publication date: July 18, 2019
    Inventors: Weiwei MAO, Hao WU, Qiang GUO, Xuejian ZHENG, Yonggang LIAO
  • Patent number: 10174036
    Abstract: A compound having the structure of below Formula (I), or pharmaceutically acceptable salts thereof, are useful as JAK inhibitors, wherein R1, R2, L1, L2, T and X are as herein described.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: January 8, 2019
    Assignee: WUXI FORTUNE PHARMACEUTICAL CO., LTD
    Inventors: Hao Wu, Peng Li, Weiwei Mao, Shuhui Chen, Fei Wang, Jian Li
  • Patent number: 10174056
    Abstract: A compound having the structure of below Formula(I), or pharmaceutically acceptable salts thereof, are useful as Janus kinase inhibitors, wherein R1 and L1 are as herein described.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: January 8, 2019
    Assignee: WUXI FORTUNE PHARMACEUTICAL CO., LTD
    Inventors: Hao Wu, Weiwei Mao, Yiqiang Huang, Lili Fan, Shuhui Chen
  • Publication number: 20180179209
    Abstract: Disclosed is a series of JAK inhibitors, which specifically relates to a compound shown in formula (I) or pharmaceutically acceptable salts thereof.
    Type: Application
    Filed: April 26, 2016
    Publication date: June 28, 2018
    Applicant: WUXI FORTUNE PHARMACEUTICAL CO., LTD
    Inventors: Hao WU, Peng LI, Weiwei MAO, Shuhui CHEN, Fei WANG, Jian LI
  • Publication number: 20180162879
    Abstract: Disclosed are a series of Janus kinase inhibitors, and particularly disclosed are a compound or pharmaceutically acceptable salts thereof of Formula (I) and use thereof in the preparation of drugs for treating Janus kinase (JAK)-related diseases.
    Type: Application
    Filed: May 26, 2016
    Publication date: June 14, 2018
    Inventors: Hao WU, Weiwei MAO, Yiqiang HUANG, Lili FAN, Shuhui CHEN
  • Patent number: 9991910
    Abstract: An apparatus for powering an electrical circuit includes a first voltage input configured to receive power from a first voltage source, a second voltage input configured to receive power from a second voltage source, wherein the second voltage source has a lower voltage than the first voltage source, a voltage regulator connected to the first voltage input, and a voltage output configured to switchably receive power from the first voltage input through the voltage regulator or from the second voltage input.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: June 5, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Weiwei Mao, Andrew Cable, Brett Hardy, Christopher John Abel
  • Publication number: 20170360794
    Abstract: The present invention discloses a series of JAK inhibitors, and particularly discloses a compound of formula (I) or a pharmaceutically acceptable salt thereof and the use thereof in preparation of drugs for treating diseases related to JAK.
    Type: Application
    Filed: January 19, 2016
    Publication date: December 21, 2017
    Applicant: WUXI FORTUNE PHARMACEUTICAL CO., LTD
    Inventors: Hao WU, Weiwei MAO, Lili FAN, Charles Z. DING, Shuhui CHEN, Fei WANG, Guoping HU, Jian LI
  • Publication number: 20170338840
    Abstract: An apparatus for powering an electrical circuit includes a first voltage input configured to receive power from a first voltage source, a second voltage input configured to receive power from a second voltage source, wherein the second voltage source has a lower voltage than the first voltage source, a voltage regulator connected to the first voltage input, and a voltage output configured to switchably receive power from the first voltage input through the voltage regulator or from the second voltage input.
    Type: Application
    Filed: May 23, 2016
    Publication date: November 23, 2017
    Inventors: Weiwei Mao, Andrew Cable, Brett Hardy, Christopher John Abel
  • Publication number: 20160142233
    Abstract: Described embodiments provide for, in a SerDes device, an adaptation process that adjusts data path gain through programmable-bias based on process, voltage, temperature (PVT) and data rate changes. Such adaptation process extends bias current dynamic range, and low frequency gain can be programmed to a desired target range of values for a given variable gain amplifier (VGA) setting at any PVT and data rate corner. A receive (RX) data path structure auto-adapts data path gain through programmable bias based on sensed PVT and data rate changes. The low frequency attenuation/gain range is extended, and can be programmed to a desirable targeted range by a SerDes device RX adaptive process for a given VGA and linear equalizer (LEQ) setting at any given PVT and data rate condition.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 19, 2016
    Applicant: LSI CORPORATION
    Inventors: Mohammad S. Mobin, Weiwei Mao, Brett D. Hardy
  • Patent number: 9325546
    Abstract: Described embodiments provide for, in a SerDes device, an adaptation process that adjusts data path gain through programmable-bias based on process, voltage, temperature (PVT) and data rate changes. Such adaptation process extends bias current dynamic range, and low frequency gain can be programmed to a desired target range of values for a given variable gain amplifier (VGA) setting at any PVT and data rate corner. A receive (RX) data path structure auto-adapts data path gain through programmable bias based on sensed PVT and data rate changes. The low frequency attenuation/gain range is extended, and can be programmed to a desirable targeted range by a SerDes device RX adaptive process for a given VGA and linear equalizer (LEQ) setting at any given PVT and data rate condition.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: April 26, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Mohammad S. Mobin, Weiwei Mao, Brett D. Hardy
  • Patent number: 9325537
    Abstract: In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: April 26, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Mohammad S. Mobin, Weiwei Mao, Chintan M. Desai, Freeman Y. Zhong, Ye Liu
  • Publication number: 20150263848
    Abstract: Described embodiments provide for, in a clock and data recovery (CDR) circuit, detection of loss of acquisition and CDR restarting with corrective integral accumulator register seeding and gearshift restarting. In described embodiments, a mechanism is employed to cause faster loss of lock condition if the CDR circuit directed on an incorrect acquisition trajectory, actual loss of CDR lock is then detected, and CDR acquisition is recovered with corrective integral accumulator seeding.
    Type: Application
    Filed: April 21, 2014
    Publication date: September 17, 2015
    Applicant: LSI Corporation
    Inventors: Mohammad S. Mobin, Weiwei Mao, Chintan M. Desai, Ye Liu
  • Publication number: 20150249555
    Abstract: In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.
    Type: Application
    Filed: April 3, 2014
    Publication date: September 3, 2015
    Applicant: LSI Corporation
    Inventors: Mohammad S. Mobin, Weiwei Mao, Chintan M. Desai, Freeman Y. Zhong, Ye Liu