Abstract: A driving method and driving device for a display panel, and a display device. The driving method includes: in a first driving stage, controlling a data voltage signal input terminal to transmit a voltage corresponding to a data voltage to a gate of a drive transistor; and in a second driving stage, controlling the data voltage signal input terminal to transmit a hold voltage to a source of the drive transistor to couple the voltage of the gate of the drive transistor through the hold voltage of the source of the drive transistor.

Abstract: A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

Abstract: A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

Abstract: A temperature sensor includes a NAND gate and a plurality of delay units. The NAND gate includes a first and a second input terminals, and an output terminal. The first input terminal is configured to receive an external starting control signal. The plurality of delay units are connected in series. An input end of the first delay unit is connected to the output terminal of the NAND gate. An output end of the last delay unit is connected to the second input terminal of the NAND gate, thereby forming a ring oscillator structure. The temperature sensor can realize conversion of temperature-leakage-frequency based on the ring oscillator structure in a temperature range of ?40˜125° C., thereby simplifying design complexity and achieves high accuracy.

Abstract: A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

Abstract: A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

Abstract: An embodiment of the present disclosure discloses an over-temperature protection circuitry and a driving method. The circuit includes a source circuit, a comparator circuit and an output circuit, wherein the comparator circuit includes a thermistor, a first resistor and a comparator, the source circuit is connected to a first input terminal of the comparator via the thermistor and is connected to a second input terminal of the comparator via the first resistor; and the comparator circuit is configured to compare a first signal from the first input terminal with a second signal from the second input terminal, and output a control signal according to a comparison result, the control signal is an over-temperature control signal in the case that the comparison result indicates that the temperature is greater than or equal to a protection threshold, and the output circuit is configured to output an disenabling signal.

Abstract: A temperature sensor includes a NAND gate and a plurality of delay units. The NAND gate includes a first and a second input terminals, and an output terminal. The first input terminal is configured to receive an external starting control signal. The plurality of delay units are connected in series. An input end of the first delay unit is connected to the output terminal of the NAND gate. An output end of the last delay unit is connected to the second input terminal of the NAND gate, thereby forming a ring oscillator structure. The temperature sensor can realize conversion of temperature-leakage-frequency based on the ring oscillator structure in a temperature range of ?40˜125° C., thereby simplifying design complexity and achieves high accuracy.

Abstract: To improve test efficiency of addressable test chips, an addressable test chip test system includes a test equipment, a probe card and an addressable test chip, the test equipment connects to the addressable test chip through the probe card to constitute a test path, the test system includes a new type of address register, which can provide two test modes for users according to user's needs. A new type of high density addressable test chip can accommodate DUTs of more than 1000/mm2.

Abstract: An addressable ring oscillator test chip includes: a plurality of ring oscillator test units, and a peripheral structure including peripheral circuits and PADs. The peripheral circuits share a first power source and a first grounding. Each test unit is associated with an independent power source to thereby decrease voltage drop resulting from wiring and to reduce the influence from other test units. A method of generating a variety of ring oscillators includes: generating a cell template corresponding to a basic unit, including defining a parameterized cell template; generating a ring oscillator based on the cell template, including generating ring oscillators of different stages by selecting different parameters of the cell template; realizing internal connections of the ring oscillator; and generating an instantiated ring oscillator by replacing cell templates with corresponding basic units.

Abstract: An embodiment of the present disclosure discloses an over-temperature protection circuitry and a driving method. The circuit includes a source circuit, a comparator circuit and an output circuit, wherein the comparator circuit includes a thermistor, a first resistor and a comparator, the source circuit is connected to a first input terminal of the comparator via the thermistor and is connected to a second input terminal of the comparator via the first resistor; and the comparator circuit is configured to compare a first signal from the first input terminal with a second signal from the second input terminal, and output a control signal according to a comparison result, the control signal is an over-temperature control signal in the case that the comparison result indicates that the temperature is greater than or equal to a protection threshold, and the output circuit is configured to output an disenabling signal.

Abstract: To improve test efficiency of addressable test chips, an addressable test chip test system includes a test equipment, a probe card and an addressable test chip, the test equipment connects to the addressable test chip through the probe card to constitute a test path, the test system includes a new type of address register, which can provide two test modes for users according to user's needs. A new type of high density addressable test chip can accommodate DUTs of more than 1000/mm2.

Abstract: An addressable test circuit is configured to test parameters of a plurality of transistors. The addressable test circuit includes combination logic circuits including a plurality of gate circuits and are configured to select a device under test, a plurality of PADs, a plurality of address bus and data bus; wherein six or more of the data buses are test signal lines. A test method can employ the above address test circuit for testing parameters of a plurality of transistors, where the subthreshold leakage current Ioff and saturation current Idsat are measured in different signal lines respectively to ensure the accurate measurement of the two parameters in one circuit.

Abstract: An addressable test circuit is configured to test parameters of a plurality of transistors. The addressable test circuit includes combination logic circuits including a plurality of gate circuits and are configured to select a device under test, a plurality of PADs, a plurality of address bus and data bus; wherein six or more of the data buses are test signal lines. A test method can employ the above address test circuit for testing parameters of a plurality of transistors, where the subthreshold leakage current Ioff and saturation current Idsat are measured in different signal lines respectively to ensure the accurate measurement of the two parameters in one circuit.

Abstract: An addressable ring oscillator test chip includes: a plurality of ring oscillator test units, and a peripheral structure including peripheral circuits and PADs. The peripheral circuits share a first power source and a first grounding. Each test unit is associated with an independent power source to thereby decrease voltage drop resulting from wiring and to reduce the influence from other test units. A method of generating a variety of ring oscillators includes: generating a cell template corresponding to a basic unit, including defining a parameterized cell template; generating a ring oscillator based on the cell template, including generating ring oscillators of different stages by selecting different parameters of the cell template; realizing internal connections of the ring oscillator; and generating an instantiated ring oscillator by replacing cell templates with corresponding basic units.

Abstract: Methods of testing key parameters of transistors can be achieved using an addressable test circuit. Saturation current and leakage current of transistor are measured through different test signal lines. The addressable test circuit can be applied to a plurality of MOS transistors, each MOS transistor has a gate end G, a drain end D, a source end S, and a substrate B, wherein the S end and D end of each MOS transistor are respectively connected to different test signal lines. The test circuit can have a high area utilization rate such that it has the capacity to put a lot of transistors within one small wafer area. In addition, each transistor's Idsat, Ioff can be measured accurately.