Patents by Inventor WEIWEI SANG

WEIWEI SANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit with embedded memory modules
    Patent number: 11587636
    Abstract: The disclosure relates to a system and method for maintaining stability during a scan shift operation on multiple embedded memories in an integrated circuit. Examples disclosed herein include an integrated circuit comprising a plurality of memory modules and a built-in self-test controller, wherein the BIST controller and memory modules are arranged and configured to reduce toggling of cells in the memory modules during a scan shift operation.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: February 21, 2023
    Assignee: NXP USA, Inc.
    Inventors: Wenbin Yang, Weiwei Sang
  • INTEGRATED CIRCUIT WITH EMBEDDED MEMORY MODULES
    Publication number: 20220199182
    Abstract: The disclosure relates to a system and method for maintaining stability during a scan shift operation on multiple embedded memories in an integrated circuit. Examples disclosed herein include an integrated circuit comprising a plurality of memory modules and a built-in self-test controller, wherein the BIST controller and memory modules are arranged and configured to reduce toggling of cells in the memory modules during a scan shift operation.
    Type: Application
    Filed: December 15, 2021
    Publication date: June 23, 2022
    Inventors: Wenbin Yang, Weiwei Sang
  • Method and apparatus for testing integrated circuit
    Patent number: 9805826
    Abstract: An integrated circuit (IC) having a memory for storing data also has a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory. A test interface provides test data. Flip-flops of the IC are connected together into at least one serial scan chain. The test interface unit receives test data including MBIST configuration data. The MBIST unit, in a first mode, tests the memory based on the MBIST configuration data at least partly in parallel with a scan test using the scan chain. Thus, both the memory and the logic circuitry can be tested in parallel.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: October 31, 2017
    Assignee: NXP USA,INC.
    Inventors: Weiwei Sang, Wanggen Zhang
  • METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUIT
    Publication number: 20160365157
    Abstract: An integrated circuit (IC) having a memory for storing data also has a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory. A test interface provides test data. Flip-flops of the IC are connected together into at least one serial scan chain. The test interface unit receives test data including MBIST configuration data. The MBIST unit, in a first mode, tests the memory based on the MBIST configuration data at least partly in parallel with a scan test using the scan chain. Thus, both the memory and the logic circuitry can be tested in parallel.
    Type: Application
    Filed: November 20, 2015
    Publication date: December 15, 2016
    Inventors: WEIWEI SANG, WANGGEN ZHANG