Patents by Inventor Weiwei Shan
Weiwei Shan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11920142Abstract: The use of a negative regulator AtRTP5 for increasing the plant resistance to Phytophthora is disclosed. The AtRTP5 gene negatively regulates the plant resistance to Phytophthora by interfering with a plant hormone immune signaling pathway. The AtRTP5 gene has a nucleotide sequence shown as SEQ ID NO: 1 or a homologous sequence having more than 50% homology with the sequence. The use of a protein encoded by a negative regulator AtRTP5 for increasing the plant resistance to Phytophthora is also disclosed. The plant resistance to Phytophthora is enhanced by reducing the expression of the protein encoded by the AtRTP5 gene with genetic engineering. The protein has an amino acid sequence shown as SEQ ID NO: 2 or a homologous sequence having more than 50% homology with the sequence.Type: GrantFiled: September 12, 2020Date of Patent: March 5, 2024Assignee: Northwest A&F UniversityInventors: Weixing Shan, Weiwei Li
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Patent number: 11715456Abstract: It discloses a serial FFT-based low-power MFCC speech feature extraction circuit, and belongs to the technical field of calculation, reckoning or counting. The circuit is oriented toward the field of intelligence, and is adapted to a hardware circuit design by optimizing an MFCC algorithm, and a serial FFT algorithm and an approximation operation on a multiplication are fully used, thereby greatly reducing a circuit area and power. The entire circuit includes a preprocessing module, a framing and windowing module, an FFT module, a Mel filtration module, and a logarithm and DCT module. The improved FFT algorithm uses a serial pipeline manner to process data, and a time of an audio frame is effectively utilized, thereby reducing a storage area and operation frequency of the circuit under the condition of meeting an output requirement.Type: GrantFiled: December 4, 2020Date of Patent: August 1, 2023Assignee: SOUTHEAST UNIVERSITYInventors: Weiwei Shan, Lixuan Zhu
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Patent number: 11664013Abstract: It discloses a speech feature reuse-based storing and calculating compression method for a keyword-spotting CNN, and belongs to the technical filed of calculating, reckoning or counting. If the updated row number of input data is equal to a convolution step size, every time new input data arrive, an input layer of a neural network replaces the earliest part of the input data with the new input data and meanwhile adjusts an addressing sequence of the input data, thereby performing an operation on the input data and corresponding convolution kernels in an arrival sequence of the input data, and an operation result is stored in an intermediate data memory of the neural network to update corresponding data.Type: GrantFiled: December 4, 2020Date of Patent: May 30, 2023Assignee: SOUTHEAST UNIVERSITYInventor: Weiwei Shan
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Patent number: 11651766Abstract: The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced.Type: GrantFiled: February 22, 2021Date of Patent: May 16, 2023Assignee: SOUTHEAST UNIVERSITYInventors: Weiwei Shan, Lixuan Zhu, Jun Yang, Longxing Shi
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Publication number: 20220189459Abstract: The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced.Type: ApplicationFiled: February 22, 2021Publication date: June 16, 2022Inventors: Weiwei SHAN, Lixuan ZHU, Jun YANG, Longxing SHI
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Patent number: 11335387Abstract: An in-memory computing circuit for a fully connected binary neural network includes an input latch circuit, a counting addressing module, an address selector, a decoding and word line drive circuit, a memory array, a pre-charge circuit, a writing bit line drive circuit, a replica bit line column cell, a timing control circuit, a sensitive amplifier and a NAND gate array, an output latch circuit and an analog delay chain. A parallel XNOR operation is performed in the circuit on the SRAM bit line, and the accumulation operation, activation operation and other operations are performed by the delay chain in the time domain. Partial calculation is completed while reading the data, and the delay chain with a small area occupation can be integrated with SRAM, thus reducing the energy consumption of the memory access process. Multi-column parallel computing also improves system throughput.Type: GrantFiled: October 30, 2019Date of Patent: May 17, 2022Assignee: SOUTHEAST UNIVERSITYInventors: Weiwei Shan, Tao Wang
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Publication number: 20210312959Abstract: An in-memory computing circuit for a fully connected binary neural network includes an input latch circuit, a counting addressing module, an address selector, a decoding and word line drive circuit, a memory array, a pre-charge circuit, a writing bit line drive circuit, a replica bit line column cell, a timing control circuit, a sensitive amplifier and a NAND gate array, an output latch circuit and an analog delay chain. A parallel XNOR operation is performed in the circuit on the SRAM bit line, and the accumulation operation, activation operation and other operations are performed by the delay chain in the time domain. Partial calculation is completed while reading the data, and the delay chain with a small area occupation can be integrated with SRAM, thus reducing the energy consumption of the memory access process. Multi-column parallel computing also improves system throughput.Type: ApplicationFiled: October 30, 2019Publication date: October 7, 2021Applicant: SOUTHEAST UNIVERSITYInventors: Weiwei SHAN, Tao WANG
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Publication number: 20210313975Abstract: A two-way adaptive clock circuit supporting a wide frequency range is composed of a phase clock generating module, a phase clock selecting module, an adaptive clock stretching or compressing amount regulating circuit module and a control module. The adaptive clock stretching or compressing amount regulating circuit module can monitor delay information of a critical path in a chip in real time and feed the information back into the control module. After receiving a clock stretching or compressing enable signal and a stretching or compressing scale signal, the control module selects a target phase clock from clocks generated by the phase clock generating module to rapidly regulate an adaptive clock in a current cycle. The present invention is applied to an adaptive voltage frequency regulating circuit based on on-line time sequence monitoring.Type: ApplicationFiled: July 9, 2019Publication date: October 7, 2021Applicant: SOUTHEAST UNIVERSITYInventors: Weiwei SHAN, Jun YANG, Longxing SHI
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Patent number: 11139805Abstract: A two-way adaptive clock circuit supporting a wide frequency range is composed of a phase clock generating module, a phase clock selecting module, an adaptive clock stretching or compressing amount regulating circuit module and a control module. The adaptive clock stretching or compressing amount regulating circuit module can monitor delay information of a critical path in a chip in real time and feed the information back into the control module. After receiving a clock stretching or compressing enable signal and a stretching or compressing scale signal, the control module selects a target phase clock from clocks generated by the phase clock generating module to rapidly regulate an adaptive clock in a current cycle. The present invention is applied to an adaptive voltage frequency regulating circuit based on on-line time sequence monitoring.Type: GrantFiled: July 9, 2019Date of Patent: October 5, 2021Assignee: SOUTHEAST UNIVERSITYInventors: Weiwei Shan, Jun Yang, Longxing Shi
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Publication number: 20210174184Abstract: The present invention discloses an ultralow-power negative margin timing monitoring method of a neural network circuit, relates to an adaptive voltage regulation technology based on on-chip timing detection, and belongs to the technical field of low-power design of integrated circuit. The present invention provides an ultralow-power operating method of neural network circuit. By inserting a timing monitoring unit in specific position of critical paths and setting partial circuits to operate under “negative margin”, the system can further lower voltage, compress the timing slack, and obtain higher power gain.Type: ApplicationFiled: February 22, 2021Publication date: June 10, 2021Inventors: Weiwei SHAN, Ziyu LI, Jun YANG, Longxing SHI
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Publication number: 20210118429Abstract: It discloses a speech feature reuse-based storing and calculating compression method for a keyword-spotting CNN, and belongs to the technical filed of calculating, reckoning or counting. If the updated row number of input data is equal to a convolution step size, every time new input data arrive, an input layer of a neural network replaces the earliest part of the input data with the new input data and meanwhile adjusts an addressing sequence of the input data, thereby performing an operation on the input data and corresponding convolution kernels in an arrival sequence of the input data, and an operation result is stored in an intermediate data memory of the neural network to update corresponding data.Type: ApplicationFiled: December 4, 2020Publication date: April 22, 2021Inventor: Weiwei SHAN
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Publication number: 20210090553Abstract: It discloses a serial FFT-based low-power MFCC speech feature extraction circuit, and belongs to the technical field of calculation, reckoning or counting. The circuit is oriented toward the field of intelligence, and is adapted to a hardware circuit design by optimizing an MFCC algorithm, and a serial FFT algorithm and an approximation operation on a multiplication are fully used, thereby greatly reducing a circuit area and power. The entire circuit includes a preprocessing module, a framing and windowing module, an FFT module, a Mel filtration module, and a logarithm and DCT module. The improved FFT algorithm uses a serial pipeline manner to process data, and a time of an audio frame is effectively utilized, thereby reducing a storage area and operation frequency of the circuit under the condition of meeting an output requirement.Type: ApplicationFiled: December 4, 2020Publication date: March 25, 2021Inventors: Weiwei SHAN, Lixuan ZHU
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Publication number: 20210089874Abstract: It discloses an ultra-low power keyword spotting neural network circuit and a method for mapping data. A neural network model used is a depthwise separable convolutional neural network, of which a weight value and an intermediate activation value are both binarized during training, to obtain a lightweight neural network model with a small memory size and a small computation quantity. The circuit is designed on the basis of a data processing unit array, utilizes a memory module to memorize a weight parameter and intermediate data of a keyword spotting neural network, data control and accuracy configuration of the data processing unit array are completed by means of a control module and a data mapping module, and the data processing unit array performs a neural network computation with hybrid accuracy; and the method for mapping the data configures.Type: ApplicationFiled: December 4, 2020Publication date: March 25, 2021Inventors: Weiwei SHAN, Boyang CHENG, Jun YANG, Longxing SHI
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Publication number: 20200332363Abstract: The disclosure related to the development of a gene expression profile to predict soft tissue sarcoma (STS) recurrence, distant metastasis, or both. Analyses identified a 36-gene gene expression profile able to accurately predict risk in a cohort of soft tissue sarcoma tumors independent of histologic and pathologic grade. This discovery offers an opportunity to enhance current staging of STS to identify patients who have a higher risk of recurring, distant metastasis, or both.Type: ApplicationFiled: June 5, 2017Publication date: October 22, 2020Applicant: Castke Bioscience, Inc.Inventors: Robert Willis COOK, Weiwei SHAN, Derek MAETZOLD
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Patent number: 10422830Abstract: A process corner detection circuit based on a self-timing ring oscillator comprises a reset circuit (1), the self-timing oscillation ring (2), and a counting module (3). The self-timing ring oscillator (2) consists of m two-input Muller C-elements and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a fabricated integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing ring oscillator (2). The number of oscillations of the self-timing ring oscillator (2) in different process corners is acquired by Hspice simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.Type: GrantFiled: December 26, 2014Date of Patent: September 24, 2019Assignee: SOUTHEAST UNIVERSITYInventors: Weiwei Shan, Longxing Shi, Jun Yang
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Patent number: 10268790Abstract: An online monitoring unit and a control circuit for ultra-wide voltage range applications are disclosed. Compared with a conventional online monitoring unit, present invention eliminates a need to reserve delay units, replaces flip-flops in the conventional online monitoring unit with a latch, and uses a transition detector with fewer transistors than that of a shadow latch in the conventional online monitoring unit, thereby reducing an area and a power consumption of the online monitoring unit significantly and improving an energy efficiency of online monitoring techniques. In addition, in the ultra-wide voltage range applications, a time borrowing property of the latch adopted by the present invention can be utilized to prevent a timing error caused by process-voltage-temperature (PVT) variations, thus enabling a minimization of a timing margin and ensuring a higher power efficiency. The present invention also discloses a control circuit for use with the online monitoring unit.Type: GrantFiled: February 24, 2017Date of Patent: April 23, 2019Assignee: Southeast UniversityInventors: Weiwei Shan, Wentao Dai, Jun Yang, Longxing Shi
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Publication number: 20180253521Abstract: An online monitoring unit and a control circuit for ultra-wide voltage range applications are disclosed. Compared with a conventional online monitoring unit, the present invention eliminates the need to reserve delay units, replaces flip-flops in the conventional online monitoring unit with a latch, and uses a transition detector with fewer transistors than that of a shadow latch in the conventional online monitoring unit, thereby reducing the area and the power consumption of the online monitoring unit significantly and improving the energy efficiency of online monitoring techniques. In addition, in the ultra-wide voltage range applications, the time borrowing property of the latch adopted by the present invention can be utilized to prevent a timing error caused by PVT variations, thus enabling the minimization of timing margin and ensuring higher power efficiency. The present invention also discloses a control circuit for use with the online monitoring unit.Type: ApplicationFiled: February 24, 2017Publication date: September 6, 2018Applicant: Southeast UniversityInventors: Weiwei SHAN, Wentao DAI, Jun YANG, Longxing SHI
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Patent number: 10033362Abstract: A PVTM-based wide voltage range clock stretching circuit is disclosed. The circuit consists of a PVTM circuit module, a phase clock generation module, a clock synchronization selection module and a control module. The PVTM circuit module monitors in real time the delay information of an on-chip delay unit to monitor the operating environment of the circuit, and feeds the delay information back to the control module. Under the control of a clock stretching enable signal and a clock stretching extent signal, the control module selects a target phase clock from the clocks generated by the phase clock generation module in accordance with the feedback from the PVTM, enabling the stretching of system clock within a single cycle in different PVT conditions. Sophisticated gate devices are not required, and the cost of area and power consumption are kept to minimal.Type: GrantFiled: February 24, 2017Date of Patent: July 24, 2018Assignee: SOUTHEAST UNIVERSITYInventors: Weiwei Shan, Liang Wan, Longxing Shi
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Publication number: 20180191335Abstract: A PVTM-based wide voltage range clock stretching circuit is disclosed. The circuit consists of a PVTM circuit module, a phase clock generation module, a clock synchronization selection module and a control module. The PVTM circuit module monitors in real time the delay information of an on-chip delay unit to monitor the operating environment of the circuit, and feeds the delay information back to the control module. Under the control of a clock stretching enable signal and a clock stretching extent signal, the control module selects a target phase clock from the clocks generated by the phase clock generation module in accordance with the feedback from the PVTM, enabling the stretching of system clock within a single cycle in different PVT conditions. Sophisticated gate devices are not required, and the cost of area and power consumption are kept to minimal.Type: ApplicationFiled: February 24, 2017Publication date: July 5, 2018Applicant: Southeast UniversityInventors: Weiwei SHAN, Liang WAN, Longxing SHI
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Publication number: 20170219649Abstract: A process corner detection circuit based on a self-timing oscillation ring comprises a reset circuit (1), the self-timing oscillation ring (2), and a counting module (3). The self-timing oscillation ring (2) consists of m two-input Miller units and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a fabricated integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing oscillation ring (2). The number of oscillations of the self-timing oscillation ring (2) in different process corners is acquired by Hspice simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.Type: ApplicationFiled: December 26, 2014Publication date: August 3, 2017Inventors: Weiwei Shan, Longxing Shi, Jun Yang