Abstract: A branch prediction circuit and a control method therefor relate to the field of computer technologies. The branch prediction circuit includes at least one branch predictor 110, where the branch predictor 110 includes a prediction information determining module 120, a readout circuit 130 and a branch prediction table 140. The prediction information determining module 120 determines target prediction information corresponding to a to-be-predicted branch instruction according to program identification information 150 corresponding to the to-be-predicted branch instruction and a branch prediction table 140; and the readout circuit 130 sends the target prediction information to a branch instruction execution and control unit 200, so that the branch instruction execution and control unit 200 performs prediction processing according to the target prediction information, and generates a prediction result corresponding to the to-be-predicted branch instruction.

Abstract: The present invention discloses a RISC processor and a method of processing flag bits of a register in the RISC processor. Said RISC processor comprises a physical register stack, an operating component connected to the physical register stack and an decoder connected to the operating component; the physical register stack comprises an emulation flag register for emulating to realize flag bits of a flag register in a CISC processor; the operating component comprises a flag read-write module for reading and writing the values of the flag bits of the emulation flag register. The operating component further comprises an operating controller for performing an operation control according to the values of the flag bits of the emulation flag register when the RISC processor is in the working mode of X86 virtual machine during an operation process.

Abstract: A RISC processor apparatus and method for supporting an X86 virtual machine.

Abstract: A multi-core processor and a frequency conversion device thereof as well as a method of communication between the cores are disclosed. Each processor core of the multi-core processor includes a frequency conversion device, which includes a multi-bit state changing means, a multiple selector, a frequency conversion coefficient register, a multi-input OR gate and a clock-gating circuit unit. A common original clock is sent to the frequency conversion device of each processor core at work. The frequency conversion device real-timely reads the value of the frequency conversion coefficient register of a corresponding processor core and receives data transmission valid signals from other processor cores. By gating the common original clock, a frequency conversion function of the processor core is completed.

Abstract: A RISC processor apparatus and method for supporting an X86 virtual machine.

Abstract: An RISC processor and a method for converting and looking-up instruction address in the RISC processor. The device comprises a decoder, which includes a look-up table module for realizing the conversion from an X86 source instruction address to an MIPS target instruction address by using a look-up table. The look-up table module includes: a looking-up sub-module for indexing the look-up table based on content, wherein if looking-up is hit, the corresponding content will be stored in a target register, and if not, an entry address of the not-hit service program will be stored in the target register; and an indexing sub-module for indexing the look-up table based on content and getting an index of the table entry in which the content resides.

Abstract: The present invention discloses a RISC processor and a method of processing flag bits of a register in the RISC processor. Said RISC processor comprises a physical register stack, an operating component connected to the physical register stack and an decoder connected to the operating component; the physical register stack comprises an emulation flag register for emulating to realize flag bits of a flag register in a CISC processor; the operating component comprises a flag read-write module for reading and writing the values of the flag bits of the emulation flag register. The operating component further comprises an operating controller for performing an operation control according to the values of the flag bits of the emulation flag register when the RISC processor is in the working mode of X86 virtual machine during an operation process.

Abstract: A multi-core processor and a frequency conversion device thereof as well as a method of communication between the cores are disclosed. Each processor core of the multi-core processor includes a frequency conversion device, which includes a multi-bit state changing means, a multiple selector, a frequency conversion coefficient register, a multi-input OR gate and a clock-gating circuit unit. A common original clock is sent to the frequency conversion device of each processor core at work. The frequency conversion device real-timely reads the value of the frequency conversion coefficient register of a corresponding processor core and receives data transmission valid signals from other processor cores. By gating the common original clock, a frequency conversion function of the processor core is completed.