Abstract: In one embodiment, a method includes receiving an input signal from a receiver, receiving a data clock (DCLK) signal, and receiving a boundary clock (BCLK) signal. The method includes, based on the input signal and the DCLK signal, recovering data from the input signal to produce a first output signal. The method includes, based on the input signal and the BCLK signal, recovering boundaries between bits in the input signal to produce a second output signal. The method includes, based on the first and second output signals, producing the DCLK and BCLK signals, with the DCLK signal being delayed with respect to the BCLK signal less than approximately 0.5 unit intervals (UIs) and greater than or equal to approximately zero UIs.

Abstract: A system for combining a plurality of signals of various phases having a wide frequency range includes a signal transmuter configured to receive a plurality of input signals of different phases. The signal transmuter is also configured to generate at least one output signal based on one or more of the input signals. The system also includes at least one switch configured to receive a control signal and operable to selectively couple at least one associated capacitor to the at least one output signal. The coupling is such that the capacitor is coupled to the at least one output signal when the switch is closed. The control signal is set to substantially reduce the saturation of the at least one output signal.

Abstract: In one embodiment, a method includes receiving an input signal from a receiver, receiving a data clock (DCLK) signal, and receiving a boundary clock (BCLK) signal. The method includes, based on the input signal and the DCLK signal, recovering data from the input signal to produce a first output signal. The method includes, based on the input signal and the BCLK signal, recovering boundaries between bits in the input signal to produce a second output signal. The method includes, based on the first and second output signals, producing the DCLK and BCLK signals, with the DCLK signal being delayed with respect to the BCLK signal less than approximately 0.5 unit intervals (UIs) and greater than or equal to approximately zero UIs.

Abstract: Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.

Abstract: A system for combining a plurality of signals of various phases having a wide frequency range includes a signal transmuter configured to receive a plurality of input signals of different phases. The signal transmuter is also configured to generate at least one output signal based on one or more of the input signals. The system also includes at least one switch configured to receive a control signal and operable to selectively couple at least one associated capacitor to the at least one output signal. The coupling is such that the capacitor is coupled to the at least one output signal when the switch is closed. The control signal is set to substantially reduce the saturation of the at least one output signal.

Abstract: A method for compensating for attenuation in an input signal includes receiving an input signal, communicating a first portion of the input signal on a first path, communicating a second portion of the input signal on a second path, and communicating a third portion of the input signal on a third path. The method also includes applying a first gain to the first portion of the input signal, applying a first-order mathematical operation and a second gain to the second portion of the input signal, and applying a second-order mathematical operation and a third gain to the portion of the input signal. The method further includes recombining the first portion, the second portion, and the third portion into an output signal.

Abstract: Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.

Abstract: Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.

Abstract: A method for correcting DC offsets in a multi-stage amplifier includes determining a DC offset imparted by a multi-stage amplifier to an input signal. The method further includes applying a correction voltage to a plurality of selected stages in the multi-stage amplifier. The total correction voltage applied substantially negates the DC offset imparted by the multi-stage amplifier.

Abstract: A method for compensating for attenuation in an input signal includes receiving an input signal, communicating a first portion of the input signal on a first path, communicating a second portion of the input signal on a second path, and communicating a third portion of the input signal on a third path. The method also includes applying a first gain to the first portion of the input signal, applying a first-order mathematical operation and a second gain to the second portion of the input signal, and applying a second-order mathematical operation and a third gain to the portion of the input signal. The method further includes recombining the first portion, the second portion, and the third portion into an output signal.

Abstract: A method for correcting DC offsets in a multi-stage amplifier includes determining a DC offset imparted by a multi-stage amplifier to an input signal. The method further includes applying a correction voltage to a plurality of selected stages in the multi-stage amplifier. The total correction voltage applied substantially negates the DC offset imparted by the multi-stage amplifier.

Abstract: Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.

Abstract: A termination system includes a termination element, a reference resistance system, and a feedback control system. The termination element includes one or more transfer gates. The transfer gates are comprised of one or more transistors that provide some resistance value that is dependent upon which transistors are in an on state or an off state. The termination element is connected to a driver system and an electrical signal line. The reference resistance system is used to provide a reference resistance value that is substantially equivalent to a line characteristic impedance of the electrical signal line. The feedback control system is connected to the reference resistance system and the termination element. The feedback control system uses the reference resistance system to generate an adjustment signal for the termination element so that the resistance value of the termination element substantially matches the line characteristic impedance of the electrical signal line.

Abstract: A phase-locked loop system that generates an output signal having low jitter includes a phase frequency detector, a charge pump, a low jitter voltage-controlled oscillator, a system low-pass filter, and a divider. The phase frequency detector couples to an input signal line. The charge pump couples to the phase frequency detector, the low jitter voltage controlled oscillator, and the low pass filter. The low-jitter voltage controlled oscillator couples to an output signal line and to the divider. The divider couples to the phase frequency detector through a feedback signal line. The low jitter voltage controlled oscillator includes a voltage regulator, a low-pass filter, and a ring oscillator. The low jitter voltage controlled oscillator may also include a current driver. The voltage regulator couples to the low-pass filter and to the input signal line. The low-pass filter couples to the optional current driver and the ring oscillator.

Abstract: A systolic linear-array modular multiplier is provided, which can perform the modular multiplication algorithm of P. L. Montgomery more efficiently. The total execution time for n-bit modular multiplication is 2n+11 cycles. The modular multiplier includes a linear array of processing elements which is constructed based on a pipeline architecture that can reduce the computation procedure by one clock period. Each of the processing elements is simple in structure, which is composed of four full adders and fourteen flip-flops. For n-bit modular multiplication, a total number of 46n+184 gates is required, which is substantially less as compared to the prior art, so that manufacturing cost of the modular multiplier can be significantly reduced. These features make the modular multiplier suitable for use in VLSI implementation of modular exponentiation which is the kernel computation in many public-key cryptosystems, such as the RSA (Rivest-Shamir-Adleman) system. With the 0.8 .mu.

Abstract: A current-mode four-quadrant analog multiplier is provided, which is constructed based on CMOS (complementary metal-oxide semiconductor) technology, capable of generating an output current signal which is proportional in magnitude to the product of two input current signals. This current-mode analog multiplier is designed based on the translinear circuit principle. The current-mode analog multiplier has high precision, wide current dynamic range, and is insensitive to temperature and process, suitable for use in VLSI implementation of many analog circuits and systems, such as fuzzy logic controllers and analog neural networks.