Patents by Inventor Weixin Kong
Weixin Kong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947889Abstract: The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.Type: GrantFiled: January 10, 2022Date of Patent: April 2, 2024Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Zhijun Fan, Zuoxing Yang, Nan Li, Wenbo Tian, Weixin Kong
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Patent number: 11949416Abstract: The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal.Type: GrantFiled: January 12, 2022Date of Patent: April 2, 2024Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Weixin Kong, Dong Yu, Wenbo Tian, Zhijun Fan, Zuoxing Yang
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Publication number: 20240039540Abstract: The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal.Type: ApplicationFiled: January 12, 2022Publication date: February 1, 2024Applicant: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Weixin KONG, Dong YU, Wenbo TIAN, Zhijun FAN, Zuoxing YANG
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Publication number: 20230342537Abstract: The present disclosure relates to a layout design method, an integrated circuit, an operation chip, and a computing device. The layout design method comprises generating a primary layout on the basis of a circuit diagram netlist by using a primary standard cell library, the circuit diagram netlist comprising a first standard cell and a second standard cell, and the primary standard cell library comprising a first standard layout of the first standard cell and a second standard layout of the second standard cell. The method further comprises consolidating the first standard layout and the second standard layout on the basis of a splicing relationship between the first standard layout and the second standard layout in the primary layout to optimize the consolidated layout.Type: ApplicationFiled: June 24, 2021Publication date: October 26, 2023Inventors: Weixin KONG, Dong YU, Zhijun FAN, Wenbo TIAN
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Patent number: 11768988Abstract: A standard unit (100) for a system on chip design includes a plurality of semiconductor devices and is configured to implement a basic logic function. The standard unit (100) includes a first transistor (110) of a first threshold type and a second transistor (120) of a second threshold type, the second threshold type is different from the first threshold type, wherein a threshold range of the first threshold type is different from that of the second threshold type.Type: GrantFiled: June 8, 2021Date of Patent: September 26, 2023Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Weixin Kong, Zuoxing Yang, Wenbo Tian, Dong Yu
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Publication number: 20230251863Abstract: A multi-bit register (200), a chip, and a computing apparatus, the multi-bit register (100) including: a plurality of register units (210-1, 210-2, . . . , 210-N), each of which is configured to store a bit of data, and the plurality of register units (210-1, 210-2, . . . , 210-N) being connected in parallel to each other; a clock buffer configured to provide a clock signal for the plurality of register units (210-1, 210-2, . . . , 210-N), wherein the plurality of register units (210-1, 210-2, . . . , 210-N) is arranged into an array of register units, and the clock buffer is arranged at an intervening position of the array of register units (210-1, 210-2, . . . , 210-N).Type: ApplicationFiled: July 7, 2021Publication date: August 10, 2023Inventors: Wenbo TIAN, Zhijun FAN, Zuoxing YANG, Nan LI, Weixin KONG
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Publication number: 20230195990Abstract: The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.Type: ApplicationFiled: January 10, 2022Publication date: June 22, 2023Inventors: Zhijun FAN, Zuoxing YANG, Nan LI, Wenbo TIAN, Weixin KONG
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Publication number: 20230195987Abstract: A standard unit (100) for a system on chip design includes a plurality of semiconductor devices and is configured to implement a basic logic function. The standard unit (100) includes a first transistor (110) of a first threshold type and a second transistor (120) of a second threshold type, the second threshold type is different from the first threshold type, wherein a threshold range of the first threshold type is different from that of the second threshold type.Type: ApplicationFiled: June 8, 2021Publication date: June 22, 2023Inventors: Weixin KONG, Zuoxing YANG, Wenbo TIAN, Dong YU
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Patent number: 11581894Abstract: Alternative data selector, a full adder, and a ripple carry adder are disclosed. The alternative data selector includes: a NOR logic circuit configured to receive a selection signal and an inverted first input and generate an intermediate result; and an AND-OR-NOT logic circuit configured to receive the selection signal, a second input, and the intermediate result of the NOR logic circuit and generate an inverted output.Type: GrantFiled: May 24, 2021Date of Patent: February 14, 2023Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Zhijun Fan, Weixin Kong, Dong Yu, Zuoxing Yang
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Patent number: 11507347Abstract: Full adder, a chip and a computing device are disclosed. A full adder includes: a plurality of primary logic cells and at least one secondary logic cell, wherein an output terminal of each primary logic cell is at least connected to an input terminal of a first secondary logic cell in the at least one secondary logic cell. The plurality of primary logic cells includes: a first primary logic cell, a second primary logic cell and a third primary logic cell respectively configured to generate a first intermediate signal, a second intermediate signal and a carry-related signal based on a first input signal, a second input signal and a carry input signal input to the full adder. Furthermore, the first secondary logic cell is configured to generate a sum output signal of the full adder based on the first intermediate signal, the second intermediate signal and the carry-related signal.Type: GrantFiled: May 14, 2021Date of Patent: November 22, 2022Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Zhijun Fan, Weixin Kong, Dong Yu, Zuoxing Yang
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Publication number: 20220269481Abstract: Full adder, a chip and a computing device are disclosed. A full adder includes: a plurality of primary logic cells and at least one secondary logic cell, wherein an output terminal of each primary logic cell is at least connected to an input terminal of a first secondary logic cell in the at least one secondary logic cell. The plurality of primary logic cells includes: a first primary logic cell, a second primary logic cell and a third primary logic cell respectively configured to generate a first intermediate signal, a second intermediate signal and a carry-related signal based on a first input signal, a second input signal and a carry input signal input to the full adder. Furthermore, the first secondary logic cell is configured to generate a sum output signal of the full adder based on the first intermediate signal, the second intermediate signal and the carry-related signal.Type: ApplicationFiled: May 14, 2021Publication date: August 25, 2022Inventors: Zhijun FAN, Weixin KONG, Dong YU, Zuoxing YANG
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Publication number: 20220271756Abstract: Alternative data selector, a full adder, and a ripple carry adder are disclosed. The alternative data selector includes: a NOR logic circuit configured to receive a selection signal and an inverted first input and generate an intermediate result; and an AND-OR-NOT logic circuit configured to receive the selection signal, a second input, and the intermediate result of the NOR logic circuit and generate an inverted output.Type: ApplicationFiled: May 24, 2021Publication date: August 25, 2022Inventors: Zhijun FAN, Weixin KONG, Dong YU, Zuoxing YANG
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Patent number: 7194243Abstract: In a direct conversion receiver with zero-frequency intermediate frequency (IF) signal, the DC offset and 1/f noise of the IF signal is compensated by means of double-sampling. The first period of the doubling-sampling is a calibration phase, which stores the DC offset and the 1/f noise. The second period is a signal flow phase during which the stored DC offset and 1/f noise is connected in opposition with the IF signal to cancel the DC offset and 1/f noise.Type: GrantFiled: April 2, 2004Date of Patent: March 20, 2007Assignee: Maryland Semiconductor Inc.Inventors: Hung C. Lin, Weixin Kong
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Publication number: 20050221781Abstract: In a direct conversion receiver with zero-frequency intermediate frequency (IF) signal, the DC offset and 1/f noise of the IF signal is compensated by means of double-sampling. The first period of the doubling-sampling is a calibration phase, which stores the DC offset and the 1/f noise. The second period is a signal flow phase during which the stored DC offset and 1/f noise is connected in opposition with the IF signal to cancel the DC offset and 1/f noise.Type: ApplicationFiled: April 2, 2004Publication date: October 6, 2005Inventors: Hung Lin, Weixin Kong