Abstract: A method for wafer-level optimization of protection circuits of nitride-based electronic device chips in a wafer is provided. The method comprises: fabricating an adjustment circuit in the wafer for each of the protection circuits, the adjustment circuit including one or more fuse elements connected respectively in parallel with one or more protection devices in the protection circuit; and adjusting each of the protection circuits by trimming one or more to-be-trimmed fuse elements corresponding to the protection circuit. The trimming of the to-be-trimmed fuse elements is performed by applying a photoresist layer on the wafer; patterning the photoresist layer with a one-to-one photomask to expose the to-be-trimmed fuse elements; and etching away the to-be-trimmed fuse elements. By using the one-to-one photomask, complete wafer coverage can be achieved without stepping the wafer repeatedly from position to position for exposure.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, a gate electrode, and a protection layer. The doped nitride-based semiconductor layer has a first portion and a second portion over the first portion and narrower than the first portion. The gate electrode is disposed over the doped nitride-based semiconductor layer and narrower than the first portion. The protection layer is disposed over the doped nitride-based semiconductor layer and the gate electrode. A top surface of the first portion of the doped nitride-based semiconductor layer is covered by the protection layer, and a sidewall of the first portion of the doped nitride-based semiconductor layer is free from coverage by the protection layer.

Abstract: A semiconductor device includes a first and a second nitride-based semiconductor layers, a gate electrode, and a doped nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The doped nitride-based semiconductor layer has a pair of opposite ledge portions free from coverage of the gate electrode and a central portion therebetween. The second nitride-based semiconductor layer has a first portion beneath the central portion and a second portion beneath the ledge portion, and the second nitride-based semiconductor layer has a doping concentration of a dopant that selected from a highly electronegative group, in which the doping concentration from the first portion to the second portion increases.

Abstract: A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, a gate electrode, a first oxynitride dielectric layer, a first passivation layer, a second oxynitride dielectric layer, a second passivation layer, and a S/D electrode. The first oxynitride dielectric layer is disposed over the second nitride-based semiconductor layer and conformally covers the doped nitride-based semiconductor layer and the gate electrode. The first passivation layer is disposed on the first oxynitride dielectric layer and in contact with the first oxynitride dielectric layer. The second oxynitride dielectric layer is disposed on the first passivation layer and in contact with the first passivation layer. The second passivation layer is disposed on the second oxynitride dielectric layer and in contact with the second oxynitride dielectric layer.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a group III-V layer disposed on the substrate, a dielectric layer disposed on the group III-V layer, and an inclined sidewall extending from the dielectric layer to the substrate. Wherein the substrate comprising a relative rough surface opposite the inclined sidewall.

Abstract: A nitride-based semiconductor device includes a first and a second nitride-based semiconductor layers, a source electrode and a drain electrode, a gate structure, a passivation layer and a field plate. The passivation layer is disposed above the second nitride-based semiconductor layer and covers the gate structure and has an enclosed air gap between the gate structure and the drain electrode. The field plate is disposed above the passivation layer and has a first portion directly over the gate structure and a second portion directly over the air gap. The second portion is separated from the air gap by at least one dielectric of the passivation layer.

Abstract: A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, a gate structure, a first passivation layer, a second passivation layer and a field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The source electrode, the drain electrode, and the gate structure are disposed above the second nitride-based semiconductor layer. The first passivation layer is disposed above the second nitride-based semiconductor layer and covers the gate structure. The second passivation layer is disposed above the first passivation layer and in a region between the source and drain electrodes. The field plate is disposed above the second passivation layer and in the region between the source electrode and drain electrode, in which the field plate contacts at least one enclosed air gap above the first passivation layer.

Abstract: A semiconductor device includes a substrate, a first GaN-based high-electron-mobility transistor (HEMT), a second GaN-based HEMT, a first interconnection, and a second interconnection is provided. The substrate has a plurality of first-type doped semiconductor regions and second-type doped semiconductor regions. The first GaN-based HEMT is disposed over the substrate to cover a first region on the first-type doped semiconductor regions and the second-type doped semiconductor regions in the substrate. The second GaN-based HEMT is disposed over the substrate to cover a second region. The first region is different from the second region. The first interconnection is disposed over and electrically connected to the substrate, forming a first interface. The second interconnection is disposed over and electrically connected to the substrate, forming a second interface. The first interface is separated from the second interface by at least two heterojunctions formed in the substrate.

Abstract: A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a group of negatively-charged ions, and a field plate. The gate electrode and the drain electrode disposed above the second nitride-based semiconductor layer to define a drift region therebetween. The group of negatively-charged ions are implanted into the drift region and spaced apart from an area directly beneath the gate and drain electrodes to form at least one high resistivity zone in the second nitride-based semiconductor layer. The field plate is disposed over the gate electrode and extends in a region between the gate electrode and the high resistivity zone.

Abstract: A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, a source electrode, a drain electrode, and a group of negatively-charged ions. The gate electrode is located between the source and drain electrodes to define a drift region between the gate and drain electrodes. A group of negatively-charged ions are implanted into the drift region and over the 2DEG region and spaced apart from the gate and drain electrodes and spaced apart from an area directly beneath the gate and drain electrodes. The gate electrode is closer to the negatively-charged ions than the drain electrode, such that the negatively-charged ions deplete at least one portion of the 2DEG region which is near the gate electrode.

Abstract: A semiconductor device includes a substrate, a first GaN-based high-electron-mobility transistor (HEMT), a second GaN-based HEMT, a first interconnection, and a second interconnection is provided. The substrate has a plurality of first-type doped semiconductor regions and second-type doped semiconductor regions. The first GaN-based HEMT is disposed over the substrate to cover a first region on the first-type doped semiconductor regions and the second-type doped semiconductor regions in the substrate. The second GaN-based HEMT is disposed over the substrate to cover a second region. The first region is different from the second region. The first interconnection is disposed over and electrically connected to the substrate, forming a first interface. The second interconnection is disposed over and electrically connected to the substrate, forming a second interface. The first interface is separated from the second interface by at least two heterojunctions formed in the substrate.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a group III-V layer disposed on the substrate, a dielectric layer disposed on the group III-V layer, and an inclined sidewall extending from the dielectric layer to the substrate. Wherein the substrate comprising a relative rough surface opposite the inclined sidewall.