Abstract: A semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer. The functional layer is located between the first electrode layer and the second electrode layer, and includes a first region and a second region having a C-shaped structure surrounding the first region. The C-shape structure opens toward a direction that is parallel with the substrate and away from the first region, that is, the C-shaped structure opens toward a distal side. The first region is made of at least germanium, and the second region includes a C-shaped ferroelectric layer and a C-shaped gate that are sequentially stacked. The C-shaped ferroelectric layer serves as a memory layer of the memory device.

Abstract: The present disclosure relates to the technical field of earphone equipment, and describes a hybrid dual unit earphone, comprising an earphone casing, an inside cavity arranged in the earphone casing, a sound output port configured to communicate with the inside cavity and provided on the earphone casing, an independent sound guiding cavity arranged in the inside cavity, wherein an opening of the sound guiding cavity is arranged toward the sound output port; a dynamic unit component comprising a dynamic speaker arranged in the inside cavity, where the sound output direction of the dynamic speaker is set towards the sound output port; a high-frequency unit component comprising a high-frequency speaker arranged in the sound guiding cavity, where the sound output direction of the high-frequency speaker is set towards the sound output port.

Abstract: A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are formed on a substrate. The semiconductor layer is etched form a sidewall to form a cavity. A channel layer is formed at the cavity and sidewalls of the first electrode layer and the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. The dummy gate layer is etched from a sidewall. The second channel part and the first channel part, which is in contact with upper and lower surfaces of the dummy gate layer are removed to form a recess. The recess is filled with a dielectric material to form an isolation sidewall.

Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.

Abstract: A semiconductor device having a ferroelectric/negative capacitor and a method of manufacturing the same, and an electronic device including the semiconductor device are provided. According to the embodiments, the semiconductor device may include: a gate electrode and a source/drain electrode formed on a substrate; a positive capacitor formed on the substrate, a first terminal of the positive capacitor being electrically connected to the gate electrode; a ferroelectric or negative capacitor formed on the substrate, a first terminal of the ferroelectric or negative capacitor being electrically connected to the gate electrode, wherein a second terminal of one of the positive capacitor and the ferroelectric or negative capacitor is electrically connected to a gate voltage application terminal, and a second terminal of the other of the positive capacitor and the ferroelectric or negative capacitor is electrically connected to the source/drain electrode.

Abstract: A semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer. The functional layer is located between the first electrode layer and the second electrode layer, and includes a first region and a second region having a C-shaped structure surrounding the first region. The C-shape structure opens toward a direction that is parallel with the substrate and away from the first region, that is, the C-shaped structure opens toward a distal side. The first region is made of at least germanium, and the second region includes a C-shaped ferroelectric layer and a C-shaped gate that are sequentially stacked. In embodiments of the present disclosure, the C-shaped ferroelectric layer serves as a memory layer of the memory device. A C-shaped channel is capable to increase an electric field within the ferroelectric layer under a fixed gate voltage, so as to increase a memory window of the semiconductor device.

Abstract: A nanowire/nanosheet device having a ferroelectric or negative capacitance material and a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device are provided. According to embodiments, the semiconductor device may include: a substrate; a nanowire/nanosheet on the substrate and spaced apart from a surface of the substrate; a gate electrode surrounding the nanowire/nanosheet; a ferroelectric or negative capacitance material layer formed on a sidewall of the gate electrode; and source/drain layers at opposite ends of the nanowire/nanosheet and adjoining the nanowire/nanosheet.

Abstract: Disclosed are a semiconductor device with a ferroelectric or negative capacitance material layer on a sidewall of a gate electrode, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to embodiments, the semiconductor device may include: a substrate; a gate electrode formed on the substrate; a ferroelectric or negative capacitance material layer formed on a sidewall of the gate electrode; and a source region and a drain region that are located on opposite sides of the gate electrode on the substrate.

Abstract: A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are sequentially formed on a substrate. Then, a part of the semiconductor layer is removed through etching a sidewall of the semiconductor layer to form a cavity. Afterwards, a channel layer is formed at the cavity, a sidewall of the first electrode layer, and a sidewall of the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. Then, a part of the dummy gate layer is removed through etching a sidewall of the dummy gate layer with the second channel part serving as a shield. Afterwards, the second channel part and the first channel part, which is in contact with an upper surface and a lower surface of the dummy gate layer, are removed to form a recess.

Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.

Abstract: The present invention relates to a process for mounting and heatsinking a piezoelectric transformer (PT). The method provides a method to mount a PT, while allowing heat generated in the device to be conducted away to the mounting surface. The method can be used in piezoelectric transformer based ballasts and power supplies such that high power levels may be achieved due to minimizing thermal constraints on the devices.

Abstract: The present invention relates to a process for mounting and heatsinking a piezoelectric transformer (PT). The method provides a method to mount a PT, while allowing heat generated in the device to be conducted away to the mounting surface. The method can be used in piezoelectric transformer based ballasts and power supplies such that high power levels may be achieved due to minimizing thermal constraints on the devices.