Patents by Inventor Wei-Yu Huang

Wei-Yu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146286
    Abstract: An integrated circuit includes a first inverter, a first transmission gate, and a second inverter constructed with wide type-one transistors and wide type-two transistors. The integrated circuit also includes a first clocked inverter and a second clocked inverter constructed with narrow type-one transistors and narrow type-two transistors. A master latch is formed with the first inverter and the first clocked inverter. A slave latch is formed with the second inverter and the second clocked inverter. The first transmission gate is coupled between the master latch and the slave latch. The wide type-one transistors are formed in a wide type-one active-region structure and the narrow type-one transistors are formed in a narrow type-one active-region structure. The wide type-two transistors are formed in a wide type-two active-region structure and the narrow type-two transistors are formed in in a narrow type-two active-region structure.
    Type: Application
    Filed: January 27, 2023
    Publication date: May 2, 2024
    Inventors: Ching-Yu HUANG, Jiann-Tyng TZENG, Wei-Cheng LIN
  • Publication number: 20240136117
    Abstract: A multi-phase coupled inductor includes a first iron core, a second iron core, and a plurality of coil windings. The first iron core includes a first body and a plurality of first core posts. The plurality of first core posts are connected to the first body. The second iron core is opposite to the first iron core. The second iron core and the first body are spaced apart from each other by a gap. The plurality of coil windings wrap around the plurality of first core posts, respectively. Each of the coil windings has at least two coils.
    Type: Application
    Filed: October 1, 2023
    Publication date: April 25, 2024
    Inventors: HUNG-CHIH LIANG, PIN-YU CHEN, HANG-CHUN LU, YA-WEN YANG, YU-TING HSU, WEI-ZHI HUANG
  • Publication number: 20240128219
    Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.
    Type: Application
    Filed: December 6, 2023
    Publication date: April 18, 2024
    Inventors: Hui-Min Huang, Wei-Hung Lin, Kai Jun Zhan, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng
  • Patent number: 11955336
    Abstract: Method of manufacturing a semiconductor device, includes forming a protective layer over substrate having a plurality of protrusions and recesses. The protective layer includes polymer composition including polymer having repeating units of one or more of: Wherein a, b, c, d, e, f, g, h, and i are each independently H, —OH, —ROH, —R(OH)2, —NH2, —NHR, —NR2, —SH, —RSH, or —R(SH)2, wherein at least one of a, b, c, d, e, f, g, h, and i on each repeating unit is not H. R, R1, and R2 are each independently a C1-C10 alkyl group, a C3-C10 cycloalkyl group, a C1-C10 hydroxyalkyl group, a C2-C10 alkoxy group, a C2-C10 alkoxy alkyl group, a C2-C10 acetyl group, a C3-C10 acetylalkyl group, a C1-C10 carboxyl group, a C2-C10 alkyl carboxyl group, or a C4-C10 cycloalkyl carboxyl group, and n is 2-1000. A resist layer is formed over the protective layer, and the resist layer is patterned.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing Hong Huang, Wei-Han Lai, Ching-Yu Chang
  • Publication number: 20240113143
    Abstract: Various embodiments of the present disclosure are directed towards an imaging device including a first image sensor element and a second image sensor element respectively comprising a pixel unit disposed within a semiconductor substrate. The first image sensor element is adjacent to the second image sensor element. A first micro-lens overlies the first image sensor element and is laterally shifted from a center of the pixel unit of the first image sensor element by a first lens shift amount. A second micro-lens overlies the second image sensor element and is laterally shifted from a center of the pixel unit of the second image sensor element by a second lens shift amount different from the first lens shift amount.
    Type: Application
    Filed: January 6, 2023
    Publication date: April 4, 2024
    Inventors: Cheng Yu Huang, Wen-Hau Wu, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Chih-Kung Chang
  • Publication number: 20240111337
    Abstract: An electronic device including a body and a receptacle connector is provided. The body has a side wall surface, a receptacle slot located at the side wall surface, a waterproof protrusion protruding from the side wall surface, and two gutters located at the side wall surface, where the waterproof protrusion is located above the receptacle slot, and the two gutters are respectively located at two opposite sides of the receptacle slot. The receptacle connector is disposed in the receptacle slot.
    Type: Application
    Filed: May 8, 2023
    Publication date: April 4, 2024
    Applicant: Acer Incorporated
    Inventors: Wei-Chih Wang, Chen-Min Hsiu, Chien-Yu Lee, Szu-Wei Yang, Fang-Ying Huang
  • Patent number: 11942464
    Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Hsiu-Jen Lin, Wei-Yu Chen, Philip Yu-Shuan Chung, Chia-Shen Cheng, Kuei-Wei Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240088182
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20240088119
    Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
  • Patent number: 11923386
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20240072021
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Publication number: 20240072115
    Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: February 13, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
  • Publication number: 20050173710
    Abstract: A method for manufacturing the light emitting diode utilizing the transparent substrate and the metal bonding technology is provided. The method includes steps of providing a growing substrate, forming a semiconductor structure on the growing substrate, forming a metal bonding layer on the semiconductor structure, bonding a transparent substrate to the semiconductor structure via the metal bonding layer, removing the growing substrate, and forming a first electrode and a second electrode on the semiconductor structure and the transparent substrate respectively.
    Type: Application
    Filed: April 11, 2005
    Publication date: August 11, 2005
    Inventors: Pan-Tzu Chang, Ying-Che Sung, Wei-Yu Huang, Chao-Min Chen, Wen-Huang Tseng
  • Publication number: 20040206963
    Abstract: A method for manufacturing the light emitting diode utilizing the transparent substrate and the metal bonding technology is provided. The method includes steps of providing a growing substrate, forming a semiconductor structure on the growing substrate, forming a metal bonding layer on the semiconductor structure, bonding a transparent substrate to the semiconductor structure via the metal bonding layer, removing the growing substrate, and forming a first electrode and a second electrode on the semiconductor structure and the transparent substrate respectively.
    Type: Application
    Filed: April 14, 2004
    Publication date: October 21, 2004
    Applicant: Arima Optoelectronics Corp.
    Inventors: Pan-Tzu Chang, Ying-Che Sung, Wei-Yu Huang, Chao-Min Chen, Wen-Huang Tseng
  • Patent number: 6728189
    Abstract: In an optical disc driver having a fixed opto-mechanic module and turntable, a disc loader includes a retractable tray for moving the optical disc into and out of the unit. The optical disc loader includes a base for mounting thereon a driving unit and a motor spinning disc; a movable tray actuated by the driving unit to linearly move into and out of the loader; a disc platform connected to the movable tray and moved therewith for loading, lifting, descending and retracting the optical disc; and a pressing unit connected to the disc platform, to be lifted and descended therewith, for pressing the optical disc to the motor spinning disc. Therefore, it saves space, simplifies the mechanism, decreases the number of components and simplifies the manufacturing process.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: April 27, 2004
    Assignee: Industrial Technology Research Institute
    Inventor: Wei-Yu Huang
  • Publication number: 20030101834
    Abstract: An anti-backlash transmission mechanism that eliminates backlashes is disclosed. An actuator is connected to a transmitted element and a driven gear. The driven gear matches with a driving gear to be receive power transmitted from the driving gear. Through the actuator, the driving gear and the driven gear match tightly in the normal state to eliminate the backlash during positioning. During transmission, the pressure between the driving gear and the driven gear decreases, lowering the friction in between.
    Type: Application
    Filed: February 5, 2002
    Publication date: June 5, 2003
    Inventor: Wei-Yu Huang
  • Publication number: 20020036968
    Abstract: In an optical disc driver having a fixed opto-mechanic module and turntable, a disc loader includes a retractable tray for moving the optical disc into and out of the unit. The optical disc loader includes a base for mounting thereon a driving unit and a motor spinning disc; a movable tray actuated by the driving unit to linearly move into and out of the loader; a disc platform connected to the movable tray and moved therewith for loading, lifting, descending and retracting the optical disc; and a pressing unit connected to the disc platform, to be lifted and descended therewith, for pressing the optical disc to the motor spinning disc. Therefore, it saves space, simplifies the mechanism, decreases the number of components and simplifies the manufacturing process.
    Type: Application
    Filed: December 13, 2000
    Publication date: March 28, 2002
    Inventor: Wei-Yu Huang