Abstract: Methods and systems are provided for single false key-controlled (SFKC) aggressive voltage scaling (AVS) and multiple parallel false key controlled (MPFKC) AVS countermeasure systems. When a plaintext value is input into a cryptographic circuit for modification by a correct key, power supplied to the cryptographic circuit is scaled based on a result of the plaintext value modified by a false key or by a random number of parallel false keys, which occurs during every clock cycle. The scaling may be triggered when the operating frequency of the cryptographic circuit falls below a threshold, which indicates occurrence of a leakage power attack. A key that is detectable within a power trace of the scaled power provided to the cryptographic circuit, with a highest correlation coefficient relative to a known key, is a key other than the correct key. The MPFKC AVS technique also inhibits unriddling of the input power scaling scheme.

Abstract: Methods and systems are provided for a charge withholding converter reshuffling technique that decorrelates input power of a multi-phase switched capacitor (SC) voltage converter relative to the output power provided to a load. The load may be a cryptographic device. The technique provides a countermeasure against power analysis attacks. A controller including a first random number generator coupled to the stages of the SC voltage converter controls gating for charging a first subset of the stages. A controller including a second random number generator coupled the stages of the SC voltage converter controls gating for discharging a second subset the stages. A number of the switched capacitor stages maintain their charge beyond the switch period in which they are charged. The SC voltage converter withholds a random portion of input charge and delivers this charge to the load after a random time period.

Abstract: Methods and systems are provided for a security adaptive (SA) voltage converter that receives input power from a power source and provides power to a cryptographic system. The SA voltage converter triggers countermeasures against leakage power analysis (LPA) attacks that slow down an operating frequency of the cryptographic circuit. When an LPA attack is detected, a discharging resistor sinks redundant current to alter the signature of load power dissipation of at the input to the SA voltage converter system. The SA voltage converter includes a converter reshuffling converter. The power dissipation induced by the discharging resistor, as measured at the input received from the power source, is scrambled by the SA voltage converter to increase noise inserted into the input power and to alter the power profile that is measured for the cryptographic circuit.

Abstract: Methods and systems are provided for single false key-controlled (SFKC) aggressive voltage scaling (AVS) and multiple parallel false key controlled (MPFKC) AVS countermeasure systems. When a plaintext value is input into a cryptographic circuit for modification by a correct key, power supplied to the cryptographic circuit is scaled based on a result of the plaintext value modified by a false key or by a random number of parallel false keys, which occurs during every clock cycle. The scaling may be triggered when the operating frequency of the cryptographic circuit falls below a threshold, which indicates occurrence of a leakage power attack. A key that is detectable within a power trace of the scaled power provided to the cryptographic circuit, with a highest correlation coefficient relative to a known key, is a key other than the correct key. The MPFKC AVS technique also inhibits unriddling of the input power scaling scheme.

Abstract: Methods and systems are provided for a charge withholding converter reshuffling technique that decorrelates input power of a multi-phase switched capacitor (SC) voltage converter relative to the output power provided to a load. The load may be a cryptographic device. The technique provides a countermeasure against power analysis attacks. A controller including a first random number generator coupled to the stages of the SC voltage converter controls gating for charging a first subset of the stages. A controller including a second random number generator coupled the stages of the SC voltage converter controls gating for discharging a second subset the stages. A number of the switched capacitor stages maintain their charge beyond the switch period in which they are charged. The SC voltage converter withholds a random portion of input charge and delivers this charge to the load after a random time period.

Abstract: Methods and systems are provided for a security adaptive (SA) voltage converter that receives input power from a power source and provides power to a cryptographic system. The SA voltage converter triggers countermeasures against leakage power analysis (LPA) attacks that slow down an operating frequency of the cryptographic circuit. When an LPA attack is detected, a discharging resistor sinks redundant current to alter the signature of load power dissipation of at the input to the SA voltage converter system. The SA voltage converter includes a converter reshuffling converter. The power dissipation induced by the discharging resistor, as measured at the input received from the power source, is scrambled by the SA voltage converter to increase noise inserted into the input power and to alter the power profile that is measured for the cryptographic circuit.

Abstract: Dynamic power management techniques and voltage converter architectures are described to provide a secure and efficient on-chip power delivery system. In aspects of the embodiments, converter-gating is used to adaptively turn individual interleaved switched-capacitor stages of a voltage converter on and off based on workload information to improve voltage conversion efficiency. Further, as a countermeasure against machine learning based differential power analysis attacks, for example, control signals provided to a number of the interleaved switched-capacitor stages are delayed to reduce the risk of low power trace entropy (PTE). A higher PTE value is maintained regardless of the phase difference between an attacker's sampling rate and the operating frequency, providing an additional layer of security.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) providing a substrate (100); b) forming a dummy gate stack on the substrate (100), wherein the dummy gate stack consists of a gate dielectric layer (203) and a dummy gate (201) located on the gate dielectric layer (203), and the material of the dummy gate (201) is amorphous Si; c) performing ion implantation to regions exposed on both sides of the dummy gate (201) on the substrate (100), so as to form source/drain regions (110); d) forming an interlayer dielectric layer (400) that covers the source/drain regions (110) and the dummy gate stack; e) removing part of the interlayer dielectric layer (400) to expose the dummy gate (201) and removing the dummy gate (201); and f) annealing to activate dopants in source/drain regions.

Abstract: The present invention provides a semiconductor structure and a method for manufacturing the same. The method comprises the following steps: providing a substrate and forming a sacrificial gate, sidewall spacers and source/drain regions located on both sides of the sacrificial gate; forming an interlayer dielectric layer that covers the device; removing the sacrificial gate to form a cavity within the sidewall spacers; forming first oxygen absorbing layers in the cavity; forming a second oxygen absorbing layer in the remaining of the space of the cavity; and performing an annealing step to make the surface of the substrate form an interfacial layer. The present invention further provides a semiconductor structure. By forming a symmetrical interfacial layer in a channel region, the present invention has reduced processing difficulty while effectively mitigating short-channel effects and preserving carrier mobility.