Abstract: The present disclosure provides a method of manufacturing semiconductor structure. The method includes providing a substrate, including an active area and an isolation surrounding the active area; forming a trench fuse in the active area; forming a gate structure of a transistor over the substrate adjacent to the trench fuse; and forming a doping region surrounding the trench fuse and the gate structure; wherein a distance between the isolation and the trench fuse is less than a distance between the isolation and the gate structure.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a transistor disposed over the substrate; and a trench fuse disposed in the substrate and penetrating a source/drain (S/D) region of the transistor. A method for manufacturing the semiconductor structure is also provided.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a well region, a fuse medium, a gate electrode, a fuse doped region, a source/drain (S/D) region, and a resistance modification doped region. The well region is within the substrate with a first conductive type. The fuse medium is disposed over the substrate. The gate electrode is disposed over the fuse medium. The fuse doped region is under the gate electrode with a second conductive type different from first conductive type. The S/D region is adjacent to the fuse doped region with the second conductive type. The resistance modification doped region has the second conductive type and partially overlaps the fuse doped region.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a well region, a fuse medium, a gate electrode, a fuse doped region, a source/drain (S/D) region, and a resistance modification doped region. The well region is within the substrate with a first conductive type. The fuse medium is disposed over the substrate. The gate electrode is disposed over the fuse medium. The fuse doped region is under the gate electrode with a second conductive type different from first conductive type. The S/D region is adjacent to the fuse doped region with the second conductive type. The resistance modification doped region has the second conductive type and partially overlaps the fuse doped region.

Abstract: A testing module includes a wafer and a probe head. The wafer includes a scribe line and a probe pad. The scribe line extends along a direction. The probe pad is disposed on the scribe line. The probe pad includes a first metal layer, a dielectric layer, and a second metal layer. The dielectric layer is disposed on the first metal layer, in which the dielectric layer includes a first recess. The second metal layer is configured to connect to the first metal layer, in which the second metal layer includes a first portion and a second portion. The first portion includes a trench exposing the dielectric layer, and the second portion is disposed on the first recess and a top surface of the dielectric layer to form a first via. The probe head includes multiple probe needles.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Abstract: This invention provides an asymmetric pads structure using at a scribe line of a wafer, comprising a test element device electrically connected to a first pad and a second pad separately, wherein a first spacing between the second pad and the test element device is sufficient to accommodate the second pad of an another asymmetric pads structure. So, two neighboring asymmetric pads structures may cross to each other to form a cross configuration.

Abstract: The present application provides a memory device. The memory device includes a semiconductor substrate including an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure disposed over the active area; a device gate structure disposed over the active area and adjacent to the fuse gate structure; and a contact plug coupled to the active area and extending away from the semiconductor substrate, wherein at least a portion of the active area is disposed under the device gate structure. Further, a method of manufacturing the memory device is also disclosed.

Abstract: A semiconductor wafer includes a scribe line and a probe pad. The scribe line extends along a first direction. The probe pad is disposed on the scribe line and is configured to contact a probe needle. The probe pad includes a first metal layer, a dielectric layer, and a second metal layer. The dielectric layer is disposed on the first metal layer, in which the dielectric layer includes a first recess and a second recess. The second metal layer is configured to connect to the first metal layer, in which the second metal layer includes a first portion and a second portion, and the first portion and the second portion are separated by a distance in a second direction perpendicular to the first direction.

Abstract: The present application discloses a semiconductor device, including a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a gate structure positioned on the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Abstract: A multi-stacking carrier structure includes an etch stop layer; a first tier comprising a first passivation layer positioned on the etch stop layer, a first insulating layer positioned on the first passivation layer, and a first via positioned along the first passivation layer and the first insulating layer; a second tier positioned on the first tier and comprising a second passivation layer positioned on the first insulating layer, a second insulating layer positioned on the second passivation layer, and a second via positioned along the second passivation layer and the second insulating layer, and electrically connected to the first via; and a third tier positioned on the second tier and comprising a third passivation layer positioned on the second insulating layer, a third insulating layer positioned on the third passivation layer, and a third via positioned along the third passivation layer and the third insulating layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive region positioned in the substrate; a first gate structure positioned on the substrate; a first drain region positioned in the substrate and adjacent to one sidewall of the first gate structure; and a first extended conductive region positioned in the substrate, under the first drain region, contacting a bottom surface of the first drain region, and distant from the bottom conductive region. A top surface of the first drain region and a top surface of the substrate are substantially coplanar. The bottom conductive region and the first extended conductive region include the same electrical type. The first drain region and the first extended conductive region include different electrical types.

Abstract: A semiconductor structure including a semiconductor substrate, an active area, a transistor gate, a fuse gate, a first dielectric pattern, a second dielectric pattern and a plurality of metal lines is provided. The active area is disposed in the semiconductor substrate. The transistor gate has a first line segment and a second line segment extending across the active area in a first direction. The fuse gate located between the first line segment and the second line segment extends across the active area in the first direction. The first dielectric pattern is disposed between the active area and the transistor gate. The second dielectric pattern is disposed between the active area and the fuse gate. The metal lines disposed on two opposite sides of the transistor gate are electrically connected to the active device.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an inter-dielectric layer on a substrate; a conductive pad in the inter-dielectric layer; and a multi-stacking carrier structure including a first tier on the inter-dielectric layer, a second tier on the first tier, and a third tier on the second tier.

Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive region positioned in the substrate; a first gate structure positioned on the substrate; a first drain region positioned in the substrate and adjacent to one sidewall of the first gate structure; and a first extended conductive region positioned in the substrate, under the first drain region, contacting a bottom surface of the first drain region, and distant from the bottom conductive region. A top surface of the first drain region and a top surface of the substrate are substantially coplanar. The bottom conductive region and the first extended conductive region include the same electrical type. The first drain region and the first extended conductive region include different electrical types.

Abstract: A semiconductor structure includes a substrate, a first fuse, a second fuse, a contact structure, and a dielectric layer. The first fuse is located in a fuse region of the substrate and includes a first fuse active region having a first portion and a second portion. The second fuse is located in the fuse region of the substrate and includes a second fuse active region having a third portion and a fourth portion. The contact structure interconnects the second portion and the third portion. The dielectric layer is located between the contact structure and the fuse region of the substrate.

Abstract: The present disclosure provides a device including a first conductive line and a second conductive line. The first conductive line includes a first segment that extends along a first direction and has a first side forming a first angle smaller than the right angle with the first direction. The second conductive line includes a first segment deviating from the first direction with the first angle. The first segment of the second conductive line is separated from the first side of the first segment of the first conductive line by a first distance greater than or equal to a first design rule distance.