Abstract: An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the guess (e.g., weak, medium or strong). The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes. Counts of the number of input weak and medium variable messages can be included in the determination of check node output messages.

Abstract: Efficient address generation for interleaver and de-interleaver. The present invention performs interleaving and de-interleaving, at opposite ends of a communication channel, by employing an efficient address generation scheme that is adaptable across a wide variety of applications and platforms. The present invention is particularly applicable to communication channels that exhibit a degree of bursty type noise. By employing interleaving and de-interleaving at the opposite ends of the communication channel, the present invention is able to offer a degree of protection against data corruption that may be caused within the communication channel. The present invention allows convolutional interleaving and de-interleaving operation on a code word by code word basis. The present invention provides for very efficient address generation for RAM based convolutional interleaving and de-interleaving.

Abstract: An implementation of an iterative decoding system within a Trellis Coded Modulation communications environment. In a disclosed embodiment of the present invention, a communication system is described wherein the transmitter uses a channel encoder (consisting of either a convolutional encoder or a block encoder) as an outer encoder. The channel encoded signal is then passed through an interleaver and provided to a Trellis Coded Modulation encoder which acts as an inner encoder. The encoded signal may then be transmitted over the channel. On the decoding side, the disclosed embodiment of the present invention advantageously applies iterative decoding steps to decode the received Trellis Coded Modulated signals, resulting in improved coding gains and a decrease in BER as compared with a conventional non-iterative approach.

Abstract: A method or apparatus for decoding of a BCH encoded signal begins by determining whether the received BCH encoded signal includes error. The decoding process continues when the received BCH encoded signal includes error by determining whether the error is correctable. This may be done by determining a number of errors of the received BCH encoded signal, identifying bit locations of the received BCH encoded signal having the error; counting the number of bit locations of the received BCH encoded signal having the error, comparing the number of errors to the number of bit locations of the received BCH encoded signal having the error, when the number of bit locations of the received BCH encoded signal having the error equals the number of errors, ceasing the identifying of the bit locations of the received BCH encoded signal having the error, and correcting information contained in the bit locations of the received BCH encoded signal having the error when the identifying of the bit locations is ceased.

Abstract: A method or apparatus for error identification of a BCH encoded signal includes processing that begins by receiving a BCH encoded signal in a binary polynomial format to produce a received polynomial. The processing then continues by converting the received polynomial into a plurality of error identifying polynomials. The processing then continues by recursively processing the plurality of binary error identifying polynomials to produce a plurality of error identifying values. The processing then continues by processing the plurality of error identifying values to produce an error locator polynomial that represents error in the received polynomial. The processing then continues by evaluating the error locator polynomial to identify the bit location of the error in the BCH encoded signal. The processing then continues by correcting the BCH encoded signal based on the bit location of the error.

Abstract: A programmable state machine of an application specific integrated circuit (ASIC) is programmed by enabling the scan mode of the integrated circuit. The process of programming the state machine continues by loading, through at least one scan chain to which the state machine is coupled, at least one timing sequence instruction into scan capable registers of the state machine. Once the at least one timing sequence instruction has been loaded into the scan capable registers, the scan mode is disabled and normal mode of the integrated circuit is resumed.

Abstract: A transceiver for an asymmetric communication system is provided that implements a buffering and scheduling scheme that utilizes a virtual clock signal to synchronize processing of asynchronous frame data for multiple ADSL sessions. In every virtual clock cycle, the transceiver first sequentially performs transmit-processes for each active ADSL line and then sequentially performs receive-processes for each active ADSL line. An Asynchronous Transfer Mode (ATM) Acceleratol provides the network interface to multiple ATM channels and communicates frame data to a Frame Buffer (FB). The FB may be used in a ping-pang fashion for the communication of data between the ATM accelerator and a Framer/Coder/Interleaver (FCI), which performs its namesake, among other, functions. The FCI also interfaces a Digital Signal Processing (DSP) core through an Interleave/De-Interleave Memory (IDIM). The DSP core generates the virtual clock signal, which schedules operation of the ATM accelerator and the FCI.

Abstract: Efficient address generation for interleaver and de-interleaver. The present invention performs interleaving and de-interleaving, at opposite ends of a communication channel, by employing an efficient address generation scheme that is adaptable across a wide variety of applications and platforms. The present invention is particularly applicable to communication channels that exhibit a degree of bursty type noise. By employing interleaving and de-interleaving at the opposite ends of the communication channel, the present invention is able to offer a degree of protection against data corruption that may be caused within the communication channel. The present invention allows convolutional interleaving and de-interleaving operation on a code word by code word basis. The present invention provides for very efficient address generation for RAM based convolutional interleaving and de-interleaving.

Abstract: A system for digital-to-analog conversion and up-conversion (frequency multiplication) that reduces the distortion and attenuation caused by the sinc effect is described. The shape of the sinc function that gives rise to the sinc effect is altered in a manner such that the distortion produced by the sinc effect is reduced. The output of a digital-to-analog converter is provided with a return-to-zero (RTZ) output such that the digital-to-analog converter produces output pulses rather than output levels as would be expected from a conventional sample-and-hold output. The use of output pulses pushes the first null of the sinc function to a relatively higher frequency and thus the sinc function does not produce as much distortion in the harmonics of the sampled signal. Since the harmonics are less distorted, a bandpass filter or other filter can be used to extract harmonics of the sampled signal rather than the fundamental frequency.

Abstract: A modulator is configured with a first multiplexer having a first data signal input coupled to receive the first digital baseband signal and a second data signal input coupled to receive the second digital baseband signal. The first multiplexer provides a multiplexed output signal including components of the first and second digital baseband signals. The modulator also includes a source of alternating samples of first and second carrier signals and a multiplier having a first input coupled to the output of the first multiplexer and a second input coupled to the source of carrier signal samples. The multiplier is thereby coupled to provide a digital modulated output signal. The source of alternating samples of first and second baseband signals may include a second multiplexer having a first signal input coupled to receive a first carrier signal and a second signal input coupled to receive a second carrier signal.

Abstract: A unique system for efficiently implementing filtered, phase shifted channels is disclosed. Instead of using separate transmit shaping filters for each channel, and modulating the filtered signals with phase-shifted carrier and one might suppose, the system phase rotates the signals for each channel and modulates such phase rotated signals with a single carrier. In addition, the system decomposes the phase rotations into 90° pre-filter portions and a post-filter portion of, for example, 45°. In an 8 channel system, such as proposed in the IS-95B standard, the channels are divided into two groups and the 90° phase rotations for each group are done at the input of the transmit shaping filters. A 45° phase rotation is then done for one of the groups at the output of the transmit shaping filter. Significantly, no multiplication is required.