Abstract: An apparatus and method for co-simulating of processors and DUT modules comprising steps of constructing and executing a processor simulation program and a Hardware Description Language (HDL) simulation environment that is activated by a corresponding simulator, and further for executing a command processing model and the processor simulation program, and establishing a message queue as a buffer of the message and data. Whenever the intercommunication occurred, the command will be processed via a Program Language Interface (PLI), the command processing model, a message queue mechanism for I/O command, and a signal mechanism for interrupt command.