Abstract: A current sensing module and a power conversion apparatus and an electronic apparatus using the same are provided. The current sensing module is suitable for detecting a first load current flowing through a first load. The current sensing module includes a sampling stage circuit and an output stage circuit. The sampling stage circuit couples across the first load and selectively exchanges coupling nodes between the sampling stage circuit and the first load by a multiplex switching means, so as to sample the first load current flowing along a first direction or a second direction, and thus generate a sampling signal. The output stage circuit is coupled to the sampling stage circuit and switches coupling nodes between the output stage circuit and the output terminal of the sampling stage circuit, so as to generate a current indication signal indicating the magnitude of the first load current according to the sampling signal.

Abstract: A current sensing module and a power conversion apparatus and an electronic apparatus using the same are provided. The current sensing module is suitable for detecting a first load current flowing through a first load. The current sensing module includes a sampling stage circuit and an output stage circuit. The sampling stage circuit couples across the first load and selectively exchanges coupling nodes between the sampling stage circuit and the first load by a multiplex switching means, so as to sample the first load current flowing along a first direction or a second direction, and thus generate a sampling signal. The output stage circuit is coupled to the sampling stage circuit and switches coupling nodes between the output stage circuit and the output terminal of the sampling stage circuit, so as to generate a current indication signal indicating the magnitude of the first load current according to the sampling signal.

Abstract: A method for receiving data is provided. Multiple packages are received according to a sliding window W(N). If a starting package of the packages is received successfully, the W(N) is slid to a W(N+1). If a non-starting package of the packages is received successfully, the corresponding counter is activated for counting. If the starting package of the packages is not successfully received and part of multiple counters counts to an up-limited value, the W(N) slides to the W(N+1). Other packages are continuously received according to the W(N+1), and whether the block sequence numbers (BSNs) of the counters located in the overlap area between the W(N) and the W(N+1) are determined. When at least one BSN to which at least one counter corresponds is not located in the overlap area, the at least one counter corresponding to the at least one BSN not located in the overlap area is reset.

Abstract: A method for receiving data is provided. Multiple packages are received according to a sliding window W(N). If a starting package of the packages is received successfully, the W(N) is slid to a W(N+1). If a non-starting package of the packages is received successfully, the corresponding counter is activated for counting. If the starting package of the packages is not successfully received and part of multiple counters counts to an up-limited value, the W(N) slides to the W(N+1). Other packages are continuously received according to the W(N+1), and whether the block sequence numbers (BSNs) of the counters located in the overlap area between the W(N) and the W(N+1) are determined. When at least one BSN to which at least one counter corresponds is not located in the overlap area, the at least one counter corresponding to the at least one BSN not located in the overlap area is reset.

Abstract: A bit-reversing method and system are disclosed for linearly scaling an image frame horizontally, vertically or both. The system includes a counter circuit for outputting the current frame-column number of the currently scanned pixel and the current frame-row number of the currently scanned frame-row. The numbers are bit reversed in a converter circuit. The bit-reversed current frame-column number is compared in a comparator circuit to a horizontal scaling constant which equals the number of pixels to be discarded in each frame-row of the image frame. The bit-reversed current frame-row number is compared in the comparator circuit to a vertical scaling constant which equals the number of frame-rows of the image frame to be discarded. If the bit-reversed current frame-row number is greater than the vertical scaling constant then the comparator circuit outputs appropriate signals to a scaling controller and an address generator for storing the currently scanned frame-row in a frame buffer.