Patents by Inventor Wen-An Liang
Wen-An Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12046293Abstract: A memory device and a method for operating selective erase scheme are provided. In an erase operation, a switch voltage is applied to at least one of a string select line or a ground select line of a selected sub-block of a selected block, a gate control voltage is applied to selected word lines of the selected sub-block, and an erase voltage is applied to bit lines and a common source line of the selected sub-block. The switch voltage is smaller than the erase voltage. The gate control voltage is smaller than the switch voltage and the erase voltage.Type: GrantFiled: August 19, 2022Date of Patent: July 23, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Chang Lu, Wen-Jer Tsai, Wei-Liang Lin
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Patent number: 11974071Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.Type: GrantFiled: August 21, 2022Date of Patent: April 30, 2024Assignee: MEDIATEK INC.Inventors: Kang-Yi Fan, Chin-Wen Liang, Chang-Chu Liu, Sheng-Hsiang Chang, You-Min Yeh
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Patent number: 11972984Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.Type: GrantFiled: December 26, 2022Date of Patent: April 30, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
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Publication number: 20240112943Abstract: A die suction assistance device is provided to a wafer. The wafer is diced into multiple dies, and a tape is taped on a bottom side of the wafer. The die suction assistance device includes a platform and multiple support structures mounted in the platform. Multiple air ducts are formed among adjacent support structures. When the wafer is air-tightly mounted on the platform, the wafer is supported by the support structures. When an external vacuum device vacuums air out of the platform, a vacuum environment with negative pressure is created in the air ducts. This allows the tape to partially separate from a backside of each of the dies towards the air ducts, and allows the dies to be picked up respectively by a suction nozzle with less chance of being damaged, securing integrities of dies.Type: ApplicationFiled: November 8, 2022Publication date: April 4, 2024Applicant: PANJIT INTERNATIONAL INC.Inventors: Chung-Hsiung HO, Chi-Hsueh LI, Wen-Liang HUANG
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Patent number: 11942993Abstract: An optical transmission device includes: a control module generate a control signal output which includes a slope adjust signal and a bias voltage offset adjust signal according to an input signal indicating a dispersion amount an electrical level adjust signal; a multi-level pulse amplitude modulator; and an asymmetrical optical modulator which is controlled by the slope adjust signal to be operated at one of a positive slope and a negative slope of a transfer function of the asymmetrical optical modulator itself, and is controlled by the bias voltage offset adjust signal of the control signal output to offset a bias voltage point of the asymmetrical optical modulator itself from a quadrature point of the transfer function, and modulates the multi-level pulse amplitude modulation signal to an optical signal to generate an optical modulate signal having a chirp.Type: GrantFiled: December 18, 2020Date of Patent: March 26, 2024Assignee: Molex, LLCInventors: Kuen-Ting Tsai, Wei-Hung Chen, Zuon-Min Chuang, Yao-Wen Liang
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Publication number: 20240094638Abstract: An optimization method for a mask pattern optical transfer includes steps as follows: First, a projection optical simulation is performed to obtain an optimal pupil configuration scheme corresponding to a virtual mask pattern. Next, a position scanning is performed to change the optimal pupil configuration scheme, so as to generate a plurality of adjusted pupil configuration schemes. A mask pattern transfer simulation is performed to obtain a plurality of pupil configuration schemes-critical dimension relationship data corresponding to the virtual mask pattern. Subsequently, an actual pupil configuration scheme suitable for an actual mask pattern is selected according to the plurality of pupil configuration schemes-critical dimension relationship data, and upon which an actual mask pattern transfer is performed.Type: ApplicationFiled: November 9, 2022Publication date: March 21, 2024Inventors: Chun-Yi CHANG, Wen-Liang HUANG
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Publication number: 20240085268Abstract: A device and method for measuring the decentration of optics under test is provided. The device comprises a rotational spindle for loading and rotating the optics under test, a light source module for providing incident light beam to the optics under test, and a wavefront sensor for receiving testing light beams with different exposures from the optics under test at a plurality of azimuthal directions.Type: ApplicationFiled: September 13, 2023Publication date: March 14, 2024Inventor: Chao-Wen Liang
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Publication number: 20240077479Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.Type: ApplicationFiled: August 10, 2023Publication date: March 7, 2024Applicant: DeepBrain Tech. IncInventors: Han-Lin Wang, Chia-Wei Chen, Yao-Wen Liang, Ting-Chun Lin, Yun-Ting Kuo, You-Yin Chen, Yu-Chun Lo, Ssu-Ju Li, Ching-Wen Chang, Yi-Chen Lin
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Publication number: 20240055045Abstract: A memory device includes a plurality of sets of bitlines, a set of data lines and a column selection circuit. Each data line is segmented into line segments separated from each other. A first data line includes a first line segment and a second line segment adjacent to each other. A second data line includes a first line segment. The column selection circuit is configured to selectively a first bitline in a first set of bitlines and a first bitline in a second set of bitlines to the first line segment and the second line segment of the first data line, respectively, and to selectively couple a second bitline in the first set of bitlines and a second bitline in the second set of bitlines to the first line segment of the second data line.Type: ApplicationFiled: August 11, 2023Publication date: February 15, 2024Inventors: WEN-LIANG CHEN, LIN MA
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Publication number: 20230397511Abstract: A dielectric isolation layer having a top surface may be formed over a substrate. A heater line, a phase change material (PCM) line, and an in-process conductive barrier plate may be formed over the dielectric isolation layer. An electrode material layer may be formed over the in-process conductive barrier plate. The electrode material layer and the in-process conductive barrier plate may be patterned such that patterned portions of the in-process conductive barrier plate include a first conductive barrier plate contacting a first area of a top surface of the PCM line, and a second conductive barrier plate contacting a second area of the top surface of the PCM line, and patterned portions of the electrode material layer include a first electrode contacting the first conductive barrier plate and a second electrode contacting the second conductive barrier plate.Type: ApplicationFiled: June 1, 2022Publication date: December 7, 2023Inventors: Harry-Hak-Lay Chuang, Chia Wen Liang, Chang-Chih Huang, Han-Yu Chen, Kuo-Chyuan Tzeng, Tsung-Hao Yeh
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Publication number: 20230288769Abstract: Disclosed herein is a solid polymer electrolyte membrane prepared by subjecting an oligomer-containing composition to a polymerization reaction. The oligomer-containing composition includes ethoxylated multifunctional acrylate monomer, polyether amine oligomer, and a lithium salt. An electrochromic device including an anode, a cathode, and the solid polymer electrolyte membrane is also disclosed. The solid polymer electrolyte membrane is disposed between the anode and the cathode.Type: ApplicationFiled: September 27, 2022Publication date: September 14, 2023Applicant: Ming Chi University of TechnologyInventors: Wen-Liang HUANG, Chun-Chen YANG
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Patent number: 11652011Abstract: A method to manufacture a semiconductor device includes: bonding a first wafer and a second wafer to be stacked vertically with one another, in which the first wafer provides a plurality of memory components and the second wafer provides a control circuit; forming a plurality of input/output channels on a surface of one of the first and second wafers; and cutting the bonded first and second wafers into a plurality of dices; wherein a plurality of first conductive contacts in the first wafer are electrically connected to the control circuit and the first conductive contacts in combinations with a plurality of first conductive vias in the first wafer form a plurality of transmission channels through which the control circuit is capable to access the memory components.Type: GrantFiled: August 12, 2021Date of Patent: May 16, 2023Assignee: AP Memory Technology Corp.Inventors: Wen Liang Chen, Lin Ma, Chien-An Yu, Chun Yi Lin
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Publication number: 20230135742Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.Type: ApplicationFiled: December 26, 2022Publication date: May 4, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
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Publication number: 20230067962Abstract: A semiconductor device includes a substrate, an isolation structure, a conductive structure, and a first contact structure. The isolation structure is disposed in the substrate. The conductive structure is disposed on the isolation structure. The conductive structure extends upwards from the isolation structure, in which the first contact structure has a top portion on the conductive structure and a bottom portion in contact with the isolation structure.Type: ApplicationFiled: August 28, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Alexander KALNITSKY, Wei-Cheng WU, Harry-Hak-Lay CHUANG, Chia Wen LIANG, Li-Feng TENG
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Patent number: 11586948Abstract: An IoT system includes a computing module for controlling an integral function of the system and including an analysis unit and a machine learning unit. The analysis unit is capable of operational analysis and creating a predictive model and creating a predictive model according to the data analyzed. The machine learning unit has an algorithm function to create a corresponding learning model. An IoT module is electrically connected to the computing module to serve as an intermediate role. At least one detection unit is electrically connected to the IoT module and disposed in soil to detect data of environmental and soil conditions and sends the data detected to the computing module for subsequent analysis.Type: GrantFiled: October 20, 2019Date of Patent: February 21, 2023Assignee: National Yang Ming Chiao Tung UniversityInventors: Wen-Liang Chen, Lung-Chieh Chen, Szu-Chia Chen, Wei-Han Chen, Chun-Yu Chu, Yu-Chi Shih, Yu-Ci Chang, Tzu-I Hsieh, Yen-Ling Chen, Li-Chi Peng, Meng-Zhan Lee, Jui-Yu Ho, Chi-Yao Ku, Nian-Ruei Deng, Yuan-Yao Chan, Erick Wang, Tai-Hsiang Yen, Shao-Yu Chiu, Jiun-Yi Lin, Yun-Wei Lin, Fung Ling Ng, Yi-Bing Lin, Chin-Cheng Wang
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Publication number: 20230034936Abstract: An optical transmission device includes: a control module generate a control signal output which includes a slope adjust signal and a bias voltage offset adjust signal according to an input signal indicating a dispersion amount an electrical level adjust signal; a multi-level pulse amplitude modulator; and an asymmetrical optical modulator which is controlled by the slope adjust signal to be operated at one of a positive slope and a negative slope of a transfer function of the asymmetrical optical modulator itself, and is controlled by the bias voltage offset adjust signal of the control signal output to offset a bias voltage point of the asymmetrical optical modulator itself from a quadrature point of the transfer function, and modulates the multi-level pulse amplitude modulation signal to an optical signal to generate an optical modulate signal having a chirp.Type: ApplicationFiled: December 18, 2020Publication date: February 2, 2023Applicant: Molex, LLCInventors: Kuen-Ting TSAI, Wei-Hung CHEN, Zuon-Min CHUANG, Yao-Wen LIANG
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Patent number: 11569133Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.Type: GrantFiled: April 27, 2020Date of Patent: January 31, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
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Patent number: 11555996Abstract: A method for analyzing 2D material thin film and a system for analyzing 2D material thin film are disclosed. The detection method includes the following steps: capturing sample images of 2D material thin films; measuring the 2D material thin films by a Raman spectrometer; performing a visible light hyperspectral algorithm on the sample images by a processor to generate a plurality of visible light hyperspectral images; performing a training and validation procedure, performing an image feature algorithm on the visible light hyperspectral images, and establishing a thin film prediction model based on a validation; and capturing a thin-film image to be measured by the optical microscope, performing the visible light hyperspectral algorithm, and then generating a distribution result of the thin-film image to be measured according to an analysis of the thin film prediction model.Type: GrantFiled: April 20, 2021Date of Patent: January 17, 2023Assignee: NATIONAL CHUNG CHENG UNIVERSITYInventors: Hsiang-Chen Wang, Kai-Chun Li, Kai-Hsiang Ke, Chun-Wen Liang
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Publication number: 20220408054Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.Type: ApplicationFiled: August 21, 2022Publication date: December 22, 2022Applicant: MEDIATEK INC.Inventors: Kang-Yi Fan, Chin-Wen Liang, Chang-Chu Liu, Sheng-Hsiang Chang, You-Min Yeh
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Patent number: D1035424Type: GrantFiled: June 16, 2022Date of Patent: July 16, 2024Assignee: BENYU CASTERS & WHEELS CO., LTDInventors: Shicong Yan, Youwei Liu, Wen Chen, Zhiru Zhou, Chuting Liang