Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a core region and an input/output (I/O) region and then forming a first metal gate on the core region and a second metal gate on the I/O region. Preferably, the first metal gate includes a first gate dielectric layer, the second metal gate includes a second gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer having different shapes such that the first gate dielectric layer includes an I-shape and the second gate dielectric layer includes a U-shape.

Abstract: A culture medium for hepatoma organoid culture, comprising an MST1/2 kinase inhibitor, at least one cell culture additive selected from N2 and B27, a hepatocyte growth factor, an ITS cell culture additive, Y27632, dexamethasone, Neuregulin-1, insulin, an epidermal cell growth factor, GlutaMAX, and non-essential amino acids. The application further relates to a hepatoma organoid culture method and an application thereof. By using the culture medium for hepatoma organoid, effective and rapid expansion of the hepatoma organoid can be achieved, and the organoid obtained by such expansion maintains the pathological characteristics of a patient, improves the culture success rate and the expansion rate of the hepatoma organoid, and provides a research basis for individualized treatment of the patient.

Abstract: A semiconductor packaging structure includes an encapsulation layer, a die, a first metal layer, a second metal layer and an electrical connection component. The die is disposed in the encapsulation layer. The first metal layer and the second metal layer are disposed in the encapsulation layer. The first metal layer and the second metal layer are disposed on opposite sides of the die, respectively. The electrical connection component is disposed in the encapsulation layer. The first metal layer is electrically connected with the second metal layer through the electrical connection component. The electrical connection component includes a non-metal core and a metal film located on a surface of the non-metal core.

Abstract: A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a memory stacking pair. The memory stacking pair includes a first memory semiconductor structure and a second memory semiconductor structure. The first memory semiconductor structure has a first front side and a first back side opposite to the first front side. The second memory semiconductor structure has a second front side and a second back side opposite to the second front side. The first memory semiconductor structure is bonded to the second memory semiconductor structure, and the first front side of the first memory semiconductor structure is proximal to the second front side of the second memory semiconductor structure, and the first back side is distal to the second back side.

Abstract: A method for handling a display control of a microprocessor in an electronic device includes: receiving a display trigger signal; and controlling a panel device in the electronic device to display a content, in response to the display trigger signal; wherein a central processing unit (CPU) in the electronic device is in a power off state, when controlling the panel device to display the content.

Abstract: A Schottky diode includes a substrate with an epitaxy layer on which a cathode region and an anode region are defined. A cathode structure and an anode structure are formed in the cathode region and the anode region respectively and horizontally separated by a distance. The anode structure includes a plurality of p-type doped regions diffused from the epitaxy layer toward the substrate, with an interval is formed between adjacent two p-type doped regions. A backside metal film and a backside protection layer are sequentially formed on a back surface of the substrate. Since the manufacturing of the Schottky diode does not involve wire bonding and molding processes, the overall thickness of the Schottky diode is reduced and heat dissipation is improved. With the backside metal film on the back side of the substrate, an equivalent resistance and a forward voltage of the Schottky diode can be reduced.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a contact etch stop layer (CESL) adjacent to the metal gate, and an interlayer dielectric (ILD) layer around the gate structure, performing a first etching process to remove the ILD layer, performing a second etching process to remove the CESL for forming a first contact hole, and then forming a first contact plug in the first contact hole. Preferably, a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug under the CESL.

Abstract: A semiconductor device includes a substrate, an isolation structure, a conductive structure, and a first contact structure. The isolation structure is disposed in the substrate. The conductive structure is disposed on the isolation structure. The conductive structure extends upwards from the isolation structure, in which the first contact structure has a top portion on the conductive structure and a bottom portion in contact with the isolation structure.

Abstract: A capacitor device is provided. The capacitor device includes a capacitor structure, a conductive line, an interlayer dielectric (ILD) and a first via conductor. The capacitor structure includes a lower electrode and an upper electrode. The conductive line is leveled with the lower electrode and electrically isolated from the lower electrode. The ILD is disposed over the capacitor structure and the conductive line. The first via conductor is adjacent to the capacitor structure and electrically coupled to the conductive line. A method for manufacturing a capacitor die is also provided.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a device layer, and a metallization structure. The substrate has a first surface. The device layer is over the first surface of the substrate. The device layer includes a plurality of passive component units. The metallization structure is over the device layer. The metallization structure includes a conductive bridge portion electrically connecting two adjacent passive component units.

Abstract: A method for decoding video data and an electronic device for performing the method are provided. The method receives the video data which includes multiple image frames. The method parses the video data to determine a first difference parameter for a first block unit within a current frame of the image frames. The method determines a first motion vector of the first block unit based on a first motion vector predictor of the first block unit, the first difference parameter, and motion vector information of one or more second block units within the current frame stored in the electronic device. The one or more second block units are adjacent to the first block unit. The method then reconstructs the first block unit based on the first motion vector and a reference frame included in the image frames.

Abstract: A method for automatically recording and transmitting a parking space number, includes judging whether vehicle speed information is lower than a preset value. When it is confirmed that the vehicle speed information is lower than the preset value, a part of vehicle surrounding images of multiple vehicle surrounding images is obtained according to gear position information of the vehicle. A parking space recognition model is established according to the multiple vehicle surrounding images and recognizing multiple characters corresponding to the part of the vehicle surrounding images. The multiple characters are grouped to form multiple sets of parking space numbers corresponding to the part of the vehicle surrounding images. A priority of the multiple sets of parking space numbers is then determined. After the vehicle is turned off, the parking space number with the highest priority in the multiple sets of parking space numbers is transmitted to a user terminal.

Abstract: A semiconductor device includes a first substrate and a second substrate. The first substrate has a plurality of first-type transistors formed of planar-type transistors or fin-type transistors, wherein a gate silicon oxide layer of each of the planar-type transistors has a first thickness, and a gate silicon oxide layer of each of the fin-type transistors has a second thickness. The second substrate is bonded to the first substrate and including a plurality of second-type transistors formed of gate-all-around (GAA) transistors, wherein a gate silicon oxide layer of each of the GAA transistors has a third thickness. The third thickness is less than the first thickness or the second thickness.

Abstract: The present invention provides a chip-based cartridge for biological detection and a detection method thereof, comprising a body formed by a flow guiding layer stacking with a substrate. The substrate has a reaction area positioned on part of the electrodes, and the reaction area is coated with a receptor for binding the detection target; The flow guiding layer has an opening aligned with the reaction area, the receptor is exposed at the opening corresponding to the body, and a microfluidic channel is formed between the flow guiding layer and the substrate; The sample is directly dropped from the opening to the reaction area to react with the receptor. After the reaction time, wash buffer is added to the sample in the reaction area. Then, the detection buffer is dropped into the reaction area so as to complete the sample detection without external driving force while improving the detection efficiency.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. Fin-shaped structures are formed by patterning a first region of a semiconductor substrate. A first shallow trench is formed in a second region of the semiconductor substrate. A part of the semiconductor substrate is exposed by a bottom of the first shallow trench. A first etching process is performed. At least a part of one of the fin-shaped structures is removed by the first etching process, and the part of the semiconductor substrate exposed by the first shallow trench is partially removed by the first etching process for forming a first deep trench. The manufacturing method of the present invention may be used to achieve the purposes of process simplification and/or manufacturing cost reduction.

Abstract: The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.

Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.

Abstract: The invention provides a semiconductor structure, the semiconductor structure comprises a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, a plurality of first metal layers located on a part of the gate structures, and the first metal layers are respectively electrically connected with the corresponding gate structures, at least one second metal layer, the second metal layer is bridged over at least two of the gate structures, wherein the depth of the first metal layer is greater than that of the second metal layer.

Abstract: A die of the package device is covered by an encapsulation layer, a plurality of lead portions are configured on the bottom surface of the encapsulation layer, a side portion of each lead portion is also exposed on a side surface of the encapsulation layer, and thereby the package device is used as a side-wettable package device; wherein, in a process of manufacturing the package device, a conductive electroplated conducting layer is formed on the surface of the encapsulation layer, and the electroplated conducting layer is used to conduct electric power required during an electroplating process. After the electroplating process is completed, the electroplated conducting layer can be used as a heat dissipation layer for the package device. The heat dissipation layer completely covers the surface of the package device so as to increase heat dissipation area and to be attached by a heat sink.