Patents by Inventor Wen-An Liang

Wen-An Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071965
    Abstract: A package includes a first package component including a semiconductor die, wherein the semiconductor die includes conductive pads, wherein the semiconductor die is surrounded by an encapsulant; an adaptive interconnect structure on the semiconductor die, wherein the adaptive interconnect structure includes conductive lines, wherein each conductive line physically and electrically contacts a respective conductive pad; and first bond pads, wherein each first bond pad physically and electrically contacts a respective conductive line; and a second package component including an interconnect structure, wherein the interconnect structure includes second bond pads, wherein each second bond pad is directly bonded to a respective first bond pad, wherein each second bond pad is laterally offset from a corresponding conductive pad which is electrically coupled to that second bond pad.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Tung-Liang Shao, Yu-Sheng Huang, Wen-Hao Cheng, Chen-Hua Yu
  • Publication number: 20240072170
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Yih-Ann Lin, Chia Ming Liang, Ryan Chia-Jen CHEN
  • Publication number: 20240055045
    Abstract: A memory device includes a plurality of sets of bitlines, a set of data lines and a column selection circuit. Each data line is segmented into line segments separated from each other. A first data line includes a first line segment and a second line segment adjacent to each other. A second data line includes a first line segment. The column selection circuit is configured to selectively a first bitline in a first set of bitlines and a first bitline in a second set of bitlines to the first line segment and the second line segment of the first data line, respectively, and to selectively couple a second bitline in the first set of bitlines and a second bitline in the second set of bitlines to the first line segment of the second data line.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 15, 2024
    Inventors: WEN-LIANG CHEN, LIN MA
  • Publication number: 20230397511
    Abstract: A dielectric isolation layer having a top surface may be formed over a substrate. A heater line, a phase change material (PCM) line, and an in-process conductive barrier plate may be formed over the dielectric isolation layer. An electrode material layer may be formed over the in-process conductive barrier plate. The electrode material layer and the in-process conductive barrier plate may be patterned such that patterned portions of the in-process conductive barrier plate include a first conductive barrier plate contacting a first area of a top surface of the PCM line, and a second conductive barrier plate contacting a second area of the top surface of the PCM line, and patterned portions of the electrode material layer include a first electrode contacting the first conductive barrier plate and a second electrode contacting the second conductive barrier plate.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Harry-Hak-Lay Chuang, Chia Wen Liang, Chang-Chih Huang, Han-Yu Chen, Kuo-Chyuan Tzeng, Tsung-Hao Yeh
  • Publication number: 20230288769
    Abstract: Disclosed herein is a solid polymer electrolyte membrane prepared by subjecting an oligomer-containing composition to a polymerization reaction. The oligomer-containing composition includes ethoxylated multifunctional acrylate monomer, polyether amine oligomer, and a lithium salt. An electrochromic device including an anode, a cathode, and the solid polymer electrolyte membrane is also disclosed. The solid polymer electrolyte membrane is disposed between the anode and the cathode.
    Type: Application
    Filed: September 27, 2022
    Publication date: September 14, 2023
    Applicant: Ming Chi University of Technology
    Inventors: Wen-Liang HUANG, Chun-Chen YANG
  • Patent number: 11652011
    Abstract: A method to manufacture a semiconductor device includes: bonding a first wafer and a second wafer to be stacked vertically with one another, in which the first wafer provides a plurality of memory components and the second wafer provides a control circuit; forming a plurality of input/output channels on a surface of one of the first and second wafers; and cutting the bonded first and second wafers into a plurality of dices; wherein a plurality of first conductive contacts in the first wafer are electrically connected to the control circuit and the first conductive contacts in combinations with a plurality of first conductive vias in the first wafer form a plurality of transmission channels through which the control circuit is capable to access the memory components.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: May 16, 2023
    Assignee: AP Memory Technology Corp.
    Inventors: Wen Liang Chen, Lin Ma, Chien-An Yu, Chun Yi Lin
  • Publication number: 20230135742
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.
    Type: Application
    Filed: December 26, 2022
    Publication date: May 4, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Publication number: 20230067962
    Abstract: A semiconductor device includes a substrate, an isolation structure, a conductive structure, and a first contact structure. The isolation structure is disposed in the substrate. The conductive structure is disposed on the isolation structure. The conductive structure extends upwards from the isolation structure, in which the first contact structure has a top portion on the conductive structure and a bottom portion in contact with the isolation structure.
    Type: Application
    Filed: August 28, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Alexander KALNITSKY, Wei-Cheng WU, Harry-Hak-Lay CHUANG, Chia Wen LIANG, Li-Feng TENG
  • Patent number: 11586948
    Abstract: An IoT system includes a computing module for controlling an integral function of the system and including an analysis unit and a machine learning unit. The analysis unit is capable of operational analysis and creating a predictive model and creating a predictive model according to the data analyzed. The machine learning unit has an algorithm function to create a corresponding learning model. An IoT module is electrically connected to the computing module to serve as an intermediate role. At least one detection unit is electrically connected to the IoT module and disposed in soil to detect data of environmental and soil conditions and sends the data detected to the computing module for subsequent analysis.
    Type: Grant
    Filed: October 20, 2019
    Date of Patent: February 21, 2023
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Wen-Liang Chen, Lung-Chieh Chen, Szu-Chia Chen, Wei-Han Chen, Chun-Yu Chu, Yu-Chi Shih, Yu-Ci Chang, Tzu-I Hsieh, Yen-Ling Chen, Li-Chi Peng, Meng-Zhan Lee, Jui-Yu Ho, Chi-Yao Ku, Nian-Ruei Deng, Yuan-Yao Chan, Erick Wang, Tai-Hsiang Yen, Shao-Yu Chiu, Jiun-Yi Lin, Yun-Wei Lin, Fung Ling Ng, Yi-Bing Lin, Chin-Cheng Wang
  • Publication number: 20230034936
    Abstract: An optical transmission device includes: a control module generate a control signal output which includes a slope adjust signal and a bias voltage offset adjust signal according to an input signal indicating a dispersion amount an electrical level adjust signal; a multi-level pulse amplitude modulator; and an asymmetrical optical modulator which is controlled by the slope adjust signal to be operated at one of a positive slope and a negative slope of a transfer function of the asymmetrical optical modulator itself, and is controlled by the bias voltage offset adjust signal of the control signal output to offset a bias voltage point of the asymmetrical optical modulator itself from a quadrature point of the transfer function, and modulates the multi-level pulse amplitude modulation signal to an optical signal to generate an optical modulate signal having a chirp.
    Type: Application
    Filed: December 18, 2020
    Publication date: February 2, 2023
    Applicant: Molex, LLC
    Inventors: Kuen-Ting TSAI, Wei-Hung CHEN, Zuon-Min CHUANG, Yao-Wen LIANG
  • Patent number: 11569133
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: January 31, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 11555996
    Abstract: A method for analyzing 2D material thin film and a system for analyzing 2D material thin film are disclosed. The detection method includes the following steps: capturing sample images of 2D material thin films; measuring the 2D material thin films by a Raman spectrometer; performing a visible light hyperspectral algorithm on the sample images by a processor to generate a plurality of visible light hyperspectral images; performing a training and validation procedure, performing an image feature algorithm on the visible light hyperspectral images, and establishing a thin film prediction model based on a validation; and capturing a thin-film image to be measured by the optical microscope, performing the visible light hyperspectral algorithm, and then generating a distribution result of the thin-film image to be measured according to an analysis of the thin film prediction model.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: January 17, 2023
    Assignee: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: Hsiang-Chen Wang, Kai-Chun Li, Kai-Hsiang Ke, Chun-Wen Liang
  • Publication number: 20220408054
    Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.
    Type: Application
    Filed: August 21, 2022
    Publication date: December 22, 2022
    Applicant: MEDIATEK INC.
    Inventors: Kang-Yi Fan, Chin-Wen Liang, Chang-Chu Liu, Sheng-Hsiang Chang, You-Min Yeh
  • Publication number: 20220344228
    Abstract: The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.
    Type: Application
    Filed: December 7, 2021
    Publication date: October 27, 2022
    Inventors: Chung-Hsiung Ho, Wei-Ming Hung, Wen-Liang Huang, Shun-Chi Shen, Chien-Chun Wang, Chi-Hsueh Li
  • Patent number: 11457173
    Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: September 27, 2022
    Assignee: MEDIATEK INC.
    Inventors: Kang-Yi Fan, Chin-Wen Liang, Chang-Chu Liu, Sheng-Hsiang Chang, You-Min Yeh
  • Publication number: 20220304157
    Abstract: A method for fabricating an assemble substrate is provided, including stacking a circuit portion on a plurality of circuit members. The circuit members are spaced apart from one another in a current packaging process to increase a layer area. The assemble substrate thus fabricated meets the requirements for a packaging substrate of a large size, and has a high yield and low fabrication cost.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 22, 2022
    Inventors: Lung-Yuan WANG, Wen-Liang Lien
  • Publication number: 20220288064
    Abstract: Provided is a novel PDGFR kinase inhibitor, comprising a compound of formula (I) or a pharmaceutically acceptable salt, solvate, ester, acid, metabolite or prodrug thereof. Further provided are use and a method of the compound of formula (I) for preventing or treating conditions associated with PDGFR kinase activity, particularly use and a method for preventing or treating conditions associated with PDGFR? and/or PDGFR? kinase activity.
    Type: Application
    Filed: August 14, 2020
    Publication date: September 15, 2022
    Applicant: HEFEI INSTITUTES OF PHYSICAL SCIENCE, CHINESE ACADEMY OF SCIENCES
    Inventors: Qing Song LIU, Jing LIU, Xi Xiang LI, Ao Li WANG, Feng Ming ZOU, Cheng CHEN, Qing Wang LIU, Juan LIU, Jiang Yan CAO, Wen Liang WANG, Shuang QI, Wen Chao WANG, Bei Lei WANG, Li WANG
  • Publication number: 20220287182
    Abstract: An embedded component structure includes a board, an electronic component, and a dielectric material layer. The board has a through cavity. The board includes an insulating core layer and a conductive member. The insulating core layer has a first surface and a second surface opposite thereto. The through cavity penetrates the insulating core layer. The conductive member extends from a portion of the first surface along a portion of the side wall of the through cavity to a portion of the second surface. The electronic component includes an electrode. The electronic component is disposed in the through cavity. The dielectric material layer is at least filled in the through cavity. The connection circuit layer covers and contacts the conductive member and the electrode. A manufacturing method of an embedded component structure is also provided.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Yu-Hua Chen, Chun-Hsien Chien, Wen-Liang Yeh, Ra-Min Tain
  • Patent number: 11411655
    Abstract: An optical receiving device includes a conversion module, a signal generation module and a control module. The conversion module performs photoelectric conversion and amplification on an optical signal to generate a photocurrent, the signal generation module provides a gain signal, performs transimpedance and amplification on the photocurrent according to an input signal indicating a preset output voltage swing to generate a voltage signal, and generates a measurement signal indicating an average optical power associated with the optical signal according to the photocurrent, the control module outputs a control signal which is variable to adjust a gain of the conversion module, so that a dynamic range of the conversion module changes as the gain of the conversion module itself changes.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: August 9, 2022
    Assignee: Molex, LLC
    Inventors: Kuen-Ting Tsai, Yao-Wen Liang, Zuon-Min Chuang, Wei-Hung Chen
  • Patent number: 11382214
    Abstract: A method for fabricating an assemble substrate is provided, including stacking a circuit portion on a plurality of circuit members. The circuit members are spaced apart from one another in a current packaging process to increase a layer area. The assemble substrate thus fabricated meets the requirements for a packaging substrate of a large size, and has a high yield and low fabrication cost.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: July 5, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lung-Yuan Wang, Wen-Liang Lien