Patents by Inventor Wen An YANG

Wen An YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978947
    Abstract: A Rugged portable device comprises: a base, a cover pivotally connected to the base, a first antenna unit, a second antenna unit, and a control unit. The first antenna unit and the second antenna unit are respectively disposed at an edge of the cover and an edge of the base, and the first antenna unit and the second antenna unit respectively have a near-field antenna and a far-field antenna. When the cover pivots relative to the base and is close to the base, the near-field antenna disposed at the cover and the near-field antenna disposed at the base generate a near-field communication (NFC) sensing signal and the near-field communication sensing signal is transmitted to the control unit. Therefore, the control unit sets up one of functions in the rugged portable device. For instance, the control unit switches off and/or switches on the far-field antenna or a peripheral unit (a keyboard or a camera).
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: May 7, 2024
    Assignee: Winmate Inc.
    Inventors: Ku-Ching Lu, Wei-Wen Yang, Hsin-Chin Wang, Chun-Yu Huang
  • Publication number: 20240142794
    Abstract: A stereo projection screen including a scattering screen having a scattering structure layer, a phase retardation layer disposed between the scattering structure layer and the polarized projector, and a metal reflection layer covering at least a part of the scattering structure layer is provided. The scattering structure layer and the phase retardation layer are arranged in a first display area and a second display area of the stereo projection screen. The metal reflection layer is arranged in at least one of the first display area and the second display area. A first image light beam having a first polarization state has a second polarization state after being transmitted to the first display area and leaving the stereo projection screen. A second image light beam having the first polarization state still has the first polarization state after being transmitted to the second display area and leaving the stereo projection screen.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Applicant: Coretronic Corporation
    Inventors: Chung-Yang Fang, Wen-Chun Wang, Bo-Han Cheng
  • Publication number: 20240145403
    Abstract: An electronic package is provided, in which electronic elements and at least one packaging module including a semiconductor chip and a shielding structure covering the semiconductor chip are disposed on a carrier structure, an encapsulation layer encapsulates the electronic elements and the packaging module, and a shielding layer is formed on the encapsulation layer and in contact with the shielding structure. Therefore, the packaging module includes the semiconductor chip and the shielding structure and has a chip function and a shielding wall function simultaneously.
    Type: Application
    Filed: February 6, 2023
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chih-Chiang HE, Ko-Wei CHANG, Chia-Yang CHEN
  • Patent number: 11973040
    Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yang Hsieh, Chien-Chang Lee, Chia-Ping Lai, Wen-Chung Lu, Cheng-Kang Huang, Mei-Shih Kuo, Alice Huang
  • Patent number: 11971435
    Abstract: The present disclosure relates to a system for automatically identifying product information, including a lamp information collection module, a controller, and a user terminal. The controller has a built-in comparison table setting different power information intervals for different lamp categories, and sends to-be-collected power information to the lamp information collection module. The lamp information collection module is used to collect corresponding power information according to the received to-be-collected power information and send the collected power information to the controller. The controller is further used to determine a category of a lamp according to the collected power information corresponding to the lamp and the power information interval comparison table, and send information of the lamp to the user terminal. The user terminal includes a human-machine interface and is used to display the information of the lamp on the human-machine interface.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: April 30, 2024
    Assignee: OPPLE LIGHTING CO., LTD.
    Inventors: Guoping Zhang, Jian Zhu, Wen Yang, Jiachun Cun
  • Publication number: 20240136291
    Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 25, 2024
    Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG
  • Publication number: 20240136117
    Abstract: A multi-phase coupled inductor includes a first iron core, a second iron core, and a plurality of coil windings. The first iron core includes a first body and a plurality of first core posts. The plurality of first core posts are connected to the first body. The second iron core is opposite to the first iron core. The second iron core and the first body are spaced apart from each other by a gap. The plurality of coil windings wrap around the plurality of first core posts, respectively. Each of the coil windings has at least two coils.
    Type: Application
    Filed: October 1, 2023
    Publication date: April 25, 2024
    Inventors: HUNG-CHIH LIANG, PIN-YU CHEN, HANG-CHUN LU, YA-WEN YANG, YU-TING HSU, WEI-ZHI HUANG
  • Publication number: 20240131498
    Abstract: The present invention relates to a SCR catalytic article, comprising —a substrate and —a copper-containing small pore zeolite, having a crystal structure characterized by a decrease of unit cell volume upon sulfurization and desulfurization of less than ?3 as determined by an X-ray powder diffraction, wherein the sulfurization and desulfurization are carried out in accordance with the processes as described in the specification, and to an exhaust treatment system comprising the same. The present invention also relates to a method for determining whether a metal-promoted small pore zeolite is resistant to irreversible sulfur poisoning and a method for evaluating whether a metal-promoted small pore zeolite is qualified for resistance to irreversible sulfur poisoning.
    Type: Application
    Filed: February 18, 2022
    Publication date: April 25, 2024
    Applicant: BASF CORPORATION
    Inventors: Jia Di Zhang, Wen-Mei Xue, Xiaofan Yang, Weiyong Tang, Burcu Bayram, Yu Fen Hao
  • Publication number: 20240133745
    Abstract: A temperature sensing device includes a substrate, a first reflective module, a first window cover, and a dual thermopile sensor. The first reflective module is disposed on the substrate, including a first mirror chamber with a narrow field of view (FOV), and the first reflective module focuses a thermal radiation from measured object to a first image plane in the first mirror chamber. The first window cover is disposed on the first reflective module, and the first window cover allows a selected band of the thermal radiation to pass through. The dual thermopile sensor is disposed on the substrate and located in the first mirror chamber, and the dual thermopile sensor senses a temperature data from the first image plane. Additional second reflective module, LED source plus pin hole with same FOV of dual thermopile sensor can illuminate the measured object for ease of placement of object to be heated.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 25, 2024
    Inventors: Chein-Hsun WANG, Ming LE, Tung-Yang LEE, Yu-Chih LIANG, Wen-Chie HUANG, Chen-Tang HUANG, Jenping KU
  • Publication number: 20240130657
    Abstract: A physiological sensing device for sensing physiological signal of an organism is provided. The physiological sensing device includes a sensing chip, a coupling sensing electrode and a coupling dielectric stacked layer. The coupling sensing electrode is electrically connected to the sensing chip. The coupling dielectric stacked layer covers the coupling sensing electrode. The coupling dielectric stacked layer is located between the coupling sensing electrode and the organism. The coupling dielectric stacked layer includes a first dielectric layer and a second dielectric layer. The dielectric constant of the second dielectric layer is greater than that of the first dielectric layer. The second dielectric layer is located between the first dielectric layer and the organism.
    Type: Application
    Filed: August 23, 2023
    Publication date: April 25, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Hsien-Wei Chiu, Tai-Jui Wang, Chieh-Wei Feng, Jui-Wen Yang
  • Patent number: 11968869
    Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: April 23, 2024
    Assignee: InnoLux Corporation
    Inventors: Ya-Wen Lin, Chien-Chih Chen, Yen-Hsi Tu, Cheng-Wei Chang, Shu-Hui Yang
  • Patent number: 11968817
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Patent number: 11963969
    Abstract: Provided is a pharmaceutical composition including gastrodin and a use thereof for the prevention or the treatment of amyotrophic lateral sclerosis. The pharmaceutical composition is effective in reducing neuronal axon degeneration and neurofibromin accumulation, improving symptoms of amyotrophic lateral sclerosis and extending life of patients of amyotrophic lateral sclerosis.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: April 23, 2024
    Assignee: BUDDHIST TZU CHI MEDICAL FOUNDATION
    Inventors: Chia-Yu Chang, Shinn-Zong Lin, Hsiao-Chien Ting, Hui-I Yang, Horng-Jyh Harn, Hong-Lin Su, Ching-Ann Liu, Yu-Shuan Chen, Tzyy-Wen Chiou, Tsung-Jung Ho
  • Publication number: 20240130050
    Abstract: An embedded circuit board, made without gas bubbles or significant internal gaps according to a manufacturing method which is provided, includes an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces and a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Inventors: Cheng-Yi Yang, Hao-Wen Zhong, Biao Li, Ming-Jaan Ho, Ning Hou
  • Patent number: 11961772
    Abstract: The present application relates to the field of semiconductor manufacturing technologies, and in particular to a method and an apparatus for automatically processing wafers. The method for automatically processing the wafers includes the following steps: providing several wafers, wherein the wafers operate on a primary path, and the primary path is a path for forming semiconductor structures on the surfaces of the wafers; determining whether there is a need for detecting defects of the wafers, and if yes, automatically switching an operating path of the wafers to a secondary path; detecting the defects of the wafers in the secondary path; and determining whether the defect detection on the wafers is finished, and if yes, automatically switching the operating path of the wafers to the primary path. The application makes it possible to automatically detect the defects of the wafers with different SWR conditions, thereby improving the automation degree of machines.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: April 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Peng Yang, Biao Gao, Li-Wei Wu, Wen-Yi Wang
  • Patent number: 11961768
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Patent number: 11957722
    Abstract: The present invention discloses an anti-aging composition, which includes: (a) isolated lactic acid bacterial strains or a fermented product thereof; and (b) an excipient, a diluent, or a carrier; wherein the isolated lactic acid bacterial strains include: Bifidobacterium bifidum VDD088 strains, Bifidobacterium breve Bv-889 strains, and Bifidobacterium longum BLI-02 strains. The present invention further provides a method for preventing aging by administering the foregoing anti-aging composition to a subject in need thereof.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: April 16, 2024
    Assignee: GLAC BIOTECH CO., LTD
    Inventors: Hsieh-Hsun Ho, Yi-Wei Kuo, Wen-Yang Lin, Jia-Hung Lin, Yen-Yu Huang, Chi-Huei Lin, Shin-Yu Tsai
  • Publication number: 20240120388
    Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.
    Type: Application
    Filed: January 18, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Jih-Sheng Yang, Shih-Chieh Chao, Chia Ming Liang, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Publication number: 20240120317
    Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.
    Type: Application
    Filed: July 13, 2023
    Publication date: April 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
  • Patent number: 11952291
    Abstract: Disclosed is a device for efficiently recycling nickel from wastewater and a method. The device includes a housing, and an extraction unit and an electro-deposition unit which are respectively arranged inside the housing. The device is reasonable in overall structural design. An oscillating and floating component and a rotating component in an extraction cavity are used to fully and uniformly mix a solution to maximize the extraction strength. A mixing component in an electro-deposition cavity is used to accelerate ion dispersion, to better recycle nickel. The device is easy to operate, low in cost and suitable for mass promotion.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: April 9, 2024
    Assignee: Chongqing University Of Arts And Sciences
    Inventors: Wei Guan, Wen Zeng, Zhongwen Ou, Dan Song, Subo Yang, Yong Zhang, Bitao Liu, Zhigang Xie