Patents by Inventor Wen-Ben Luo

Wen-Ben Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Gate structure with low resistance for high power semiconductor devices
    Patent number: 7589377
    Abstract: In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: September 15, 2009
    Assignee: The Boeing Company
    Inventors: Mercedes P. Gomez, Emil M. Hanna, Wen-Ben Luo, Qingchun Zhang
  • Novel Gate Structure with Low Resistance for High Power Semiconductor Devices
    Publication number: 20080085591
    Abstract: In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.
    Type: Application
    Filed: October 6, 2006
    Publication date: April 10, 2008
    Inventors: Mercedes P. Gomez, Emil M. Hanna, Wen-Ben Luo, Qingchun Zhang