Abstract: An input/output circuit includes a first switch element, a control voltage providing circuit and a floating voltage providing circuit. The first switch element includes a control terminal, a first path terminal, a second path terminal and a base terminal. The first path terminal receive a first voltage, and the second path terminal receives a second voltage. The control voltage providing circuit provides a control voltage to the control terminal of the first switch element. The floating voltage providing circuit provides the larger between the first voltage and the second voltage to the base terminal of the first switch element, so as to prevent a leakage current from being generated between the first voltage source or the second voltage source and the base terminal of the first switch element.

Abstract: An input/output circuit includes a first switch element, a control voltage providing circuit and a floating voltage providing circuit. The first switch element includes a control terminal, a first path terminal, a second path terminal and a base terminal. The first path terminal receive a first voltage, and the second path terminal receives a second voltage. The control voltage providing circuit provides a control voltage to the control terminal of the first switch element. The floating voltage providing circuit provides the larger between the first voltage and the second voltage to the base terminal of the first switch element, so as to prevent a leakage current from being generated between the first voltage source or the second voltage source and the base terminal of the first switch element.

Abstract: An eye pattern measurement apparatus includes: an eye pattern monitoring device, performing first sampling on a data signal by sequentially using scan clock signals having different phases to obtain a plurality of scan data signals; and a data aligning device, connected to the eye pattern monitoring device, receiving the scan data signals outputted by the eye pattern monitoring device, performing phase-shift on the first clock signal to generate a synchronization clock signal, synchronizing the scan data signals with the synchronization clock signal, and outputting the synchronized scan data signals.

Abstract: A processing method and electronic apparatus for a digital signal are provided. The method includes: detecting the quality of a first eye in an eye diagram of the digital signal; equalizing the digital signal; detecting the quality of a second eye in the eye diagram of the equalized digital signal; determining whether the quality of the second eye superior to the quality of the first eye by a predetermined threshold; and if so, outputting the digital signal, or else again equalizing and performing subsequent steps on the auto-compensated digital signal. The above solution is capable of effectively improving the quality of eyes in the eye diagram of the digital signal.

Abstract: An eye pattern measurement apparatus includes: an eye pattern monitoring device, performing first sampling on a data signal by sequentially using scan clock signals having different phases to obtain a plurality of scan data signals; and a data aligning device, connected to the eye pattern monitoring device, receiving the scan data signals outputted by the eye pattern monitoring device, performing phase-shift on the first clock signal to generate a synchronization clock signal, synchronizing the scan data signals with the synchronization clock signal, and outputting the synchronized scan data signals.

Abstract: A processing method and electronic apparatus for a digital signal are provided. The method includes: detecting the quality of a first eye in an eye diagram of the digital signal; equalizing the digital signal; detecting the quality of a second eye in the eye diagram of the equalized digital signal; determining whether the quality of the second eye superior to the quality of the first eye by a predetermined threshold; and if so, outputting the digital signal, or else again equalizing and performing subsequent steps on the auto-compensated digital signal. The above solution is capable of effectively improving the quality of eyes in the eye diagram of the digital signal.

Abstract: A analog equalizer includes: an adjusting circuit, generating an adjustment signal and a selection signal; a cascaded equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, a tunable capacitor and a tunable current source in the multi-stage equalization circuit according to the adjustment signal to perform an equalization process on a signal to be equalized; and an analog multiplexer, coupled to the cascaded equalization circuit and the adjusting circuit, selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit according to the selection signal. Wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.

Abstract: A analog equalizer includes: an adjusting circuit, generating an adjustment signal and a selection signal; a cascaded equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, a tunable capacitor and a tunable current source in the multi-stage equalization circuit according to the adjustment signal to perform an equalization process on a signal to be equalized; and an analog multiplexer, coupled to the cascaded equalization circuit and the adjusting circuit, selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit according to the selection signal. Wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.

Abstract: A dual phase-locked loop (PLL) circuit includes a phase/frequency detector, a charge pump, a frequency tuning circuit and an N divider. The frequency tuning circuit includes a coarse-tuning circuit, for coarse-tuning an output frequency of the dual PLL circuit to approximate a target frequency; a fine-tuning circuit, for fine-tuning the output frequency of the dual PLL circuit to the target frequency; and a current control oscillator (CCO), for generating an output signal of the dual PLL circuit. The output frequency of the output signal is equal to the target frequency.

Abstract: A dual phase-locked loop (PLL) circuit includes a phase/frequency detector, a charge pump, a frequency tuning circuit and an N divider. The frequency tuning circuit includes a coarse-tuning circuit, for coarse-tuning an output frequency of the dual PLL circuit to approximate a target frequency; a fine-tuning circuit, for fine-tuning the output frequency of the dual PLL circuit to the target frequency; and a current control oscillator (CCO), for generating an output signal of the dual PLL circuit. The output frequency of the output signal is equal to the target frequency.

Abstract: A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.

Abstract: A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.