Abstract: An interconnect structure on a semiconductor die includes: a lower conductive layer; an upper conductive layer disposed above the lower conductive layer; and a VIA disposed between the lower conductive layer and the upper conductive layer. The VIA includes: a primary interconnect structure and a sacrificial stress barrier ring disposed around the primary interconnect structure and separated a distance from the primary interconnect structure. A fabrication method for the interconnect structure includes: forming a dielectric layer over a lower conductive layer; patterning photoresist (PR) layer over the dielectric layer to define a location for a plurality of VIA trenches, wherein the patterning includes patterning the PR layer to provide a center opening for the VIA trenches that is surrounded by a ring opening for the VIA trenches, wherein the center opening and the ring opening are spaced apart.

Abstract: A surface processing device includes a machining mechanism and a driving mechanism driving the machining mechanism to polish a workpiece. The machining mechanism includes a machining assembly and a first transmission shaft eccentrically coupled with the machining assembly at a first end. The first transmission shaft rotates to bring the machining assembly into revolving around the first transmission shaft. The driving mechanism includes a motor connected to a second end of the first transmission shaft for outputting power to the machining mechanism. The surface processing device provides smooth machining without the noise of a pneumatically-powered tool.