Abstract: The present provides two low offset voltage AlInAs/GaInAs heterostructure-confinement bipolar transistors which include AlInAs heterostructure-confinement and AlInAs/GaInAs superlattice-confinement bipolar transistors. In the present invention, an n GaInAs emitter layer is inserted at AlGaAs confinement layer/GaInAs base layer to reduce offset voltage and potential spike at an E-B junction.

Abstract: The present invention provides a GaInP/GaInAs/GaAs modulation-compositioned channel field-effect transistor which comprises: a substrate of semi-insulated GaAs material; a first layer of non-doped GaAs material, formed on the substrate; a second layer of n-doped GaInAs material, formed on the first layer; a third layer of non-doped GaInP material, formed on the second layer; a fourth layer of n-doped GaAs material, formed on the third layer; an Au layer, formed on the third layer; and an Au/Ge/Ni alloy layer, formed on the fourth layer. An accumulation effect is performed because there is a V-shaped energy band existing in the modulation-compositioned channel. Therefore, the transistor of the present invention is characterized by a large current density, a large gate voltage swing with high transconductance, and a high gate breakdown voltage. The present invention has a good potentiality for high-speed, high-power, and large input signal circuit applications.

Abstract: The present invention provides a structure of a metal-insulator-semiconductor (MIS)-like multiple-negative-differential-resistance (MNDR) device and the fabrication method thereof. The device of the present invention has the characteristics of dual-route and MNDR at low temperatures. These characteristics result from the successive barrier-lowering and potential-redistribution effect when conducting carriers fall into a quantum well. MNDR devices have excellent potential in multiple-value logic circuitry applications and are capable of reducing circuitry complexity.

Abstract: A new high-speed resonant tunneling device, namely, a long-period superlattice resonant tunneling transistor, is developed according to the invention. The structure of the proposed 20-period superlattice resonant tunneling transistor consists of an InP substrate, a buffer layer formed by GaInAs material on the substrate, a collector layer formed by GaInAs material on the buffer layer, a base layer formed by GaInAs material on the collector layer, an emitter layer formed by GaInAs material on the base, a 20-period superlattice resonant tunneling layer formed by AlInAs and GaInAs materials on the emitter layer, and an ohmic contact layer formed by GaInAs material on the 20-period superlattice resonant tunneling layer. Furthermore, the emitter region includes a 20-period AlInAs/GaInAs superlattice and an emitter layer. Due to the presence of an emitter-base homojunction, collector-emitter offset voltage (V.sub.CE,offset) can be reduced significantly. In addition, the valence band discontinuity (.DELTA.

Abstract: The invention relates to the structure of the camel-gate field-effect transistor with multiple modulation-doped channels. The device structure, from the bottom to the top in succession, includes the substrate, the buffer layer, the multiple modulation-doped channels, the thin and complete depletion layer, and the ohmic contact layer. The transistor is characterized by a camel-gate diode, which is composed of the multiple modulation-doped channels, the thin and complete depletion layer and the ohmic contact layer. The gate structure may achieve the high potential height between the gate electrode and the source electrode as well as the high breakdown voltage performance. Furthermore, the use of multiple modulation-doped channels, made of n-type GaAs materials with different thickness and doped concentration, can exhibit excellent properties of high output current, large and linear transconductances.

Abstract: A pseudomorphic step-doped-channel field-effect transistor is provided, which has advantages of large transconductance, high electron mobility, high gate voltage swing and high current density, and can increase the pinch-off voltage tolerance. Thus the pseudomorphic step-doped-channel field-effect transistor is suitable for high-speed, high-power, and large-input signal circuitry systems. The pseudomorphic step-doped-channel field-effect transistor comprises: a semi-insulating GaAs substrate; an undoped GaAs layer formed on the GaAs substrate to serve as a buffer layer; an n-doping InGaAs layer formed on the undoped GaAs layer to serve as a channel layer; an undoped AlGaAs layer formed on the n-doping InGaAs layer to serve as a Schottky contact layer; an n-doping GaAs layer formed on the undoped AlGaAs layer; and metal layers formed on the undoped AlGaAs layer and the n-doping GaAs layer to respectively serve as a gate, a drain and a source of the pseudomorphic step-doped-channel field-effect transistor.

Abstract: The invention presents a structure of heterostructure-emitter and heterostructure-base transistor. The device structure are, from bottom upward in succession, a substrate, a buffer layer, a collector layer, a base layer, a quantum well, an emitter layer, a confinement layer and an ohmic contact layer. Of them, except the quantum well which is made of InGaAs and the confinement layer which is formed by AlGaAs, the rest are all made of GaAs material. Base on the design of the heterostructure of base and emitter, a transistor of such structure, under normal operation mode, possesses high current gain and low offset voltage so as to reduce undesirable power consumption. In addition, under the inverted operation mode, the interesting multiple S-shaped negative-differential-resistance may be obtained due to the avalanche multiplication and two-stage carrier confinement effects.