Patents by Inventor Wen Che
Wen Che has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250140644Abstract: A contact structure according to the present disclosure includes a conductive feature, an etch stop layer (ESL) over the conductive feature, a dielectric layer over the ESL, and a contact feature extending through the dielectric layer and the ESL to contact the conductive feature. The dielectric layer includes a low-k dielectric matrix material, and nano-pipes disposed in the low-k dielectric matrix material and configured to reduce a thermal resistance of the dielectric layer.Type: ApplicationFiled: January 25, 2024Publication date: May 1, 2025Inventors: Ming-Hsien Lin, Wen-Che Liao, Kun-Yen Liao, Hsiao-Kang Chang
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Patent number: 12288822Abstract: A semiconductor device includes a substrate, an epitaxial structure over the substrate, a conductive structure, and a dielectric liner. The conductive structure extends from within the epitaxial structure to above the epitaxial structure. The dielectric liner extends along a sidewall of the conductive structure. The dielectric liner has a top end capped by the conductive structure.Type: GrantFiled: June 21, 2023Date of Patent: April 29, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua-Feng Chen, Kuo-Hua Pan
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Publication number: 20250079538Abstract: An electronic device and a battery management method thereof are provided. The method includes the following. A battery learning enable command is received to execute a battery learning operation. During an execution period of the battery learning operation, usage record data of a battery module is analyzed to obtain usage situation information. An appropriate value of a charging limit capacity is determined based on the usage situation information.Type: ApplicationFiled: May 24, 2024Publication date: March 6, 2025Applicant: ASUSTeK COMPUTER INC.Inventors: Chunyen Lai, Chun Tsao, Wen-Che Chung, Ying-Yui Wu
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Patent number: 12242321Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: GrantFiled: April 27, 2023Date of Patent: March 4, 2025Assignee: ASUSTEK COMPUTER INC.Inventors: Wen Che Chung, Hui Chuan Lo, Hao-Hsuan Lin, Chun Tsao, Jun-Fu Chen, Ming-Hung Yao, Jia-Wei Zhang, Kuan-Lun Chen, Ting-Chao Lin, Cheng-Yen Lin, Chunyen Lai
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Publication number: 20250011923Abstract: The present invention provides a method for preparing a boron nitride thin film and the boron nitride thin film itself. The method primarily includes providing a precursor containing boron and nitrogen atoms to an energy control apparatus and forming an excited state of the precursor within this energy control apparatus. Finally, a material layer is formed on a substrate, where this material layer comprises boron nitride. The key feature of this method is the use of an energy control apparatus that includes a first electromagnetic wave source emitting electromagnetic waves within a specific wavelength range. The advantage of this method is that it can be operated at lower temperatures, reducing the risk of thermal damage to the substrate and also decreasing energy consumption. Additionally, the method includes several optional steps that can further enhance the formation of the boron nitride thin film.Type: ApplicationFiled: July 5, 2024Publication date: January 9, 2025Inventors: Wen-Che Kuo, Wen-Lian Lee, Hao-Chun Lee, Yuan-Liang Kuo, Chien-Ho Liu, Ming-Sin Tsai
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Publication number: 20240363318Abstract: A fabrication system for fabricating IC is provided. A processing tool includes a RF sensor. The RF sensor wirelessly detects intensity of a RF signal. A computation device extracts statistical characteristics with a sampling rate. When the detected intensity of the RF signal exceeds a threshold value or a threshold range, a fault detection and classification (FDC) system notifies the processing tool to adjust the RF signal or stop tool to check parts damage.Type: ApplicationFiled: July 8, 2024Publication date: October 31, 2024Inventors: Wun-Kai TSAI, Wen-Che LIANG, Chao-Keng LI, Zheng-Jie XU, Chih-Kuo CHANG, Sing-Tsung LI, Feng-Kuang WU, Hsu-Shui LIU
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Patent number: 12057301Abstract: A fabrication system for fabricating IC is provided. A processing tool includes at least one electrode and a RF sensor. The electrode is configured to receive a radio frequency (RF) signal from an RF signal generator during first and second semiconductor manufacturing processes. The RF sensor wirelessly detects intensity of the RF signal. A computation device extracts statistical characteristics with a sampling rate based on the detected intensity of the RF signal. A fault detection and classification (FDC) system includes a processor. The processor is configured to determine whether or not the detected intensity of the RF signal exceeds a threshold value or a threshold range according to the extracted statistical characteristics. When the detected intensity of the RF signal exceeds the threshold value or the threshold range, the processor notifies the processing tool to adjust the RF signal or stop tool to check parts damage.Type: GrantFiled: April 18, 2023Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wun-Kai Tsai, Wen-Che Liang, Chao-Keng Li, Zheng-Jie Xu, Chih-Kuo Chang, Sing-Tsung Li, Feng-Kuang Wu, Hsu-Shui Liu
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Patent number: 12039232Abstract: A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.Type: GrantFiled: December 24, 2020Date of Patent: July 16, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chun-An Lin, Wen-Che Shen, Chih-Wei Yeh, Po-Huan Chou, Chun-Chieh Chang, Yu-Hsun Wu
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Publication number: 20240222194Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.Type: ApplicationFiled: March 14, 2024Publication date: July 4, 2024Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Song-Bor Lee, Wen-Hsiung Lu, Po-Hao Tsai, Wen-Che Chang
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Patent number: 11961762Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.Type: GrantFiled: June 30, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Song-Bor Lee, Wen-Hsiung Lu, Po-Hao Tsai, Wen-Che Chang
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Publication number: 20240113345Abstract: A battery module and a short protection method thereof are provided. The battery module has a battery cell pack and a control circuit. The method includes: detecting a temperature of the battery cell pack as a battery cell temperature through the control circuit; determining whether the battery cell temperature shows a downward trend when the battery cell temperature is higher than a first predetermined temperature value; and deactivating the battery module when the battery cell temperature does not show the downward trend.Type: ApplicationFiled: May 23, 2023Publication date: April 4, 2024Applicant: ASUSTeK COMPUTER INC.Inventors: Chunyen Lai, Yu-Cheng Shen, Chun Tsao, Chaochan Tan, Huichuan Lo, Wen-Che Chung, Ming Hung Yao
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Publication number: 20240069618Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: ApplicationFiled: April 27, 2023Publication date: February 29, 2024Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
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Publication number: 20240049396Abstract: A method for manufacturing a semi-flex printed circuit board is provided, including: forming two convex metal dam structures and two concave laser cut grooves on a side surface of the core substrate; wherein inner sides of the two metal dam structures form a printing area at the side surface of the core substrate, and the positions of the two laser cut grooves correspond to the printing area; printing a strippable printing ink in the printing area on the core substrate; laminating a build-up board structure on the side surface of the core substrate; and forming two blind routing openings on another side surface of the core substrate, which correspond to the two laser cut grooves in position respectively; removing a cover-opening structure of the core substrate between the two blind routing openings, so as to form a cover-opening opening.Type: ApplicationFiled: August 2, 2023Publication date: February 8, 2024Applicant: TRIPOD (WUXI) ELECTRONIC CO., LTD.Inventors: Cheng Ming LU, Han-Ching SHIH, Hsu TU, Wen-Che CHEN, Wu-Chiang MA
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Publication number: 20240049401Abstract: A semi-flex printed circuit board with cover-opening opening is disclosed. An inner side of the core substrate surrounds a cover-opening opening. The two metal dam structures are arranged on a side surface of the core substrate; and the two metal dam structures and the core substrate jointly surround the cover-opening opening. The core board is arranged on a side surface of the bonding sheet away from the core substrate. Two sides of a bottom of the core substrate surrounding the cover-opening opening are provided with two laser cutting sidewalls respectively. Sidewalls of the two metal dam structures surrounding the cover-opening opening are connected with the two laser cutting sidewalls respectively and each defined as a metal dam sidewall. An obtuse angle presents between the metal dam sidewall and the laser cutting sidewall.Type: ApplicationFiled: August 2, 2023Publication date: February 8, 2024Applicant: TRIPOD (WUXI) ELECTRONIC CO., LTD.Inventors: Cheng Ming LU, Han-Ching SHIH, Hsu TU, Wen-Che CHEN, Wu-Chiang MA
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Publication number: 20230386904Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.Type: ApplicationFiled: July 27, 2023Publication date: November 30, 2023Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
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Patent number: 11804402Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.Type: GrantFiled: December 29, 2020Date of Patent: October 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
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Publication number: 20230335643Abstract: A semiconductor device includes a substrate, an epitaxial structure over the substrate, a conductive structure, and a dielectric liner. The conductive structure extends from within the epitaxial structure to above the epitaxial structure. The dielectric liner extends along a sidewall of the conductive structure. The dielectric liner has a top end capped by the conductive structure.Type: ApplicationFiled: June 21, 2023Publication date: October 19, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che TSAI, Min-Yann HSIEH, Hua-Feng CHEN, Kuo-Hua PAN
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Patent number: 11752104Abstract: An oral composition includes an immediate-release pharmaceutical admixture and an extended-release pharmaceutical admixture. The immediate-release pharmaceutical admixture includes a first portion of an active ingredient and a first portion of a hydrophilic dispersant, in which the active ingredient is substantially insoluble in water. The extended-release pharmaceutical admixture includes a controlled-release material, a second portion of the active ingredient, and a second portion of the hydrophilic dispersant, wherein the second portion of the active ingredient and the second portion of the hydrophilic dispersant are mixed in the controlled-release material, wherein the active ingredient is present as a nanoparticle in the immediate-release pharmaceutical admixture and the extended-release pharmaceutical admixture.Type: GrantFiled: May 29, 2020Date of Patent: September 12, 2023Assignee: MEDICAL AND PHARMACEUTICAL INDUSTRY TECHNOLOGY ANDInventors: Meng-Kun Tsai, Chih-Chiang Yang, Wen-Che Wang, Tzu-Yu Chien, Chien-Chia Wu, Lai-Cheng Chin
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Publication number: 20230253195Abstract: A fabrication system for fabricating IC is provided. A processing tool includes at least one electrode and a RF sensor. The electrode is configured to receive a radio frequency (RF) signal from an RF signal generator during first and second semiconductor manufacturing processes. The RF sensor wirelessly detects intensity of the RF signal. A computation device extracts statistical characteristics with a sampling rate based on the detected intensity of the RF signal. A fault detection and classification (FDC) system includes a processor. The processor is configured to determine whether or not the detected intensity of the RF signal exceeds a threshold value or a threshold range according to the extracted statistical characteristics. When the detected intensity of the RF signal exceeds the threshold value or the threshold range, the processor notifies the processing tool to adjust the RF signal or stop tool to check parts damage.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Wun-Kai TSAI, Wen-Che LIANG, Chao-Keng LI, Zheng-Jie XU, Chih-Kuo CHANG, Sing-Tsung LI, Feng-Kuang WU, Hsu-Shui LIU
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Patent number: 11721763Abstract: A method comprises forming a source/drain region on a substrate; forming a dielectric layer over the source/drain region; forming a contact hole in the dielectric layer; forming a contact hole liner in the contact hole; removing a first portion of the contact hole liner to expose a sidewall of the contact hole; etching the exposed sidewall of the contact hole to laterally expand the contact hole; and forming a contact plug in the laterally expanded contact hole.Type: GrantFiled: December 17, 2020Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua-Feng Chen, Kuo-Hua Pan