Patents by Inventor Wen-Che Tsai
Wen-Che Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961762Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.Type: GrantFiled: June 30, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Song-Bor Lee, Wen-Hsiung Lu, Po-Hao Tsai, Wen-Che Chang
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Publication number: 20230386904Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.Type: ApplicationFiled: July 27, 2023Publication date: November 30, 2023Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
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Patent number: 11804402Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.Type: GrantFiled: December 29, 2020Date of Patent: October 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
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Publication number: 20230335643Abstract: A semiconductor device includes a substrate, an epitaxial structure over the substrate, a conductive structure, and a dielectric liner. The conductive structure extends from within the epitaxial structure to above the epitaxial structure. The dielectric liner extends along a sidewall of the conductive structure. The dielectric liner has a top end capped by the conductive structure.Type: ApplicationFiled: June 21, 2023Publication date: October 19, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che TSAI, Min-Yann HSIEH, Hua-Feng CHEN, Kuo-Hua PAN
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Patent number: 11721763Abstract: A method comprises forming a source/drain region on a substrate; forming a dielectric layer over the source/drain region; forming a contact hole in the dielectric layer; forming a contact hole liner in the contact hole; removing a first portion of the contact hole liner to expose a sidewall of the contact hole; etching the exposed sidewall of the contact hole to laterally expand the contact hole; and forming a contact plug in the laterally expanded contact hole.Type: GrantFiled: December 17, 2020Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua-Feng Chen, Kuo-Hua Pan
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Patent number: 11251181Abstract: Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth.Type: GrantFiled: December 16, 2019Date of Patent: February 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
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Publication number: 20210143277Abstract: A method comprises forming a source/drain region on a substrate; forming a dielectric layer over the source/drain region; forming a contact hole in the dielectric layer; forming a contact hole liner in the contact hole; removing a first portion of the contact hole liner to expose a sidewall of the contact hole; etching the exposed sidewall of the contact hole to laterally expand the contact hole; and forming a contact plug in the laterally expanded contact hole.Type: ApplicationFiled: December 17, 2020Publication date: May 13, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che TSAI, Min-Yann HSIEH, Hua-Feng CHEN, Kuo-Hua PAN
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Publication number: 20210118723Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.Type: ApplicationFiled: December 29, 2020Publication date: April 22, 2021Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
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Patent number: 10879110Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.Type: GrantFiled: September 10, 2018Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
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Patent number: 10872980Abstract: A semiconductor device includes a substrate, an inter-layer dielectric layer, a contact plug, and a contact hole liner. The substrate has a source/drain region. The inter-layer dielectric layer is over the substrate and has a contact hole therein. The contact plug is electrically connected to the source/drain region through the contact hole of the inter-layer dielectric layer. The contact hole liner extends between the contact plug and a sidewall of a first portion of the contact hole. The contact hole liner terminates prior to reaching a second portion of the contact hole. The first portion is between the second portion and the source/drain region.Type: GrantFiled: April 25, 2017Date of Patent: December 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua-Feng Chen, Kuo-Hua Pan
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Publication number: 20200119007Abstract: Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
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Patent number: 10510751Abstract: Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth.Type: GrantFiled: August 25, 2017Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
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Patent number: 10332786Abstract: A method for manufacturing a semiconductor device includes forming a gate stack over a substrate; forming an interlayer dielectric over the substrate to cover the gate stack; forming an opening in the interlayer dielectric to expose to the gate stack; forming a glue layer over the interlayer dielectric and in the opening; partially removing the glue layer, in which a portion of the glue layer remain in the opening; and tuning a profile of the remained portion of the glue layer.Type: GrantFiled: June 12, 2017Date of Patent: June 25, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua-Feng Chen, Kuo-Hua Pan
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Publication number: 20190096740Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.Type: ApplicationFiled: September 10, 2018Publication date: March 28, 2019Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
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Publication number: 20190067276Abstract: Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth.Type: ApplicationFiled: August 25, 2017Publication date: February 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
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Publication number: 20190027959Abstract: A power supply apparatus including a first rectifier switching circuit and a second rectifier switching circuit is provided. The first rectifier switching circuit is coupled between a live wire terminal and a neutral wire terminal of a first AC power and a first contact and a second contact. The second rectifier switching circuit is coupled between a live wire terminal and a neutral wire terminal of a second AC power and the first contact and the second contact. The first rectifier switching circuit performs rectification on the first AC power and thereby provides a rectified power to the first contact and the second contact when a status of the first AC power is normal. The second rectifier switching circuit performs rectification on the second AC power and thereby provides the rectified power to the first contact and the second contact when the status of the first AC power is abnormal.Type: ApplicationFiled: May 14, 2018Publication date: January 24, 2019Applicant: Lite-On Technology CorporationInventors: Yong-Long Lee, Wen-Che Tsai, Shih-Ming Chen
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Publication number: 20180315646Abstract: A method for manufacturing a semiconductor device includes forming a gate stack over a substrate; forming an interlayer dielectric over the substrate to cover the gate stack; forming an opening in the interlayer dielectric to expose to the gate stack; forming a glue layer over the interlayer dielectric and in the opening; partially removing the glue layer, in which a portion of the glue layer remain in the opening; and tuning a profile of the remained portion of the glue layer.Type: ApplicationFiled: June 12, 2017Publication date: November 1, 2018Inventors: Wen-Che TSAI, Min-Yann HSIEH, Hua-Feng CHEN, Kuo-Hua PAN
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Publication number: 20180308797Abstract: A semiconductor device includes a substrate, an inter-layer dielectric layer, a contact plug, and a contact hole liner. The substrate has a source/drain region. The inter-layer dielectric layer is over the substrate and has a contact hole therein. The contact plug is electrically connected to the source/drain region through the contact hole of the inter-layer dielectric layer. The contact hole liner extends between the contact plug and a sidewall of a first portion of the contact hole. The contact hole liner terminates prior to reaching a second portion of the contact hole. The first portion is between the second portion and the source/drain region.Type: ApplicationFiled: April 25, 2017Publication date: October 25, 2018Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua-Feng Chen, Kuo-Hua Pan
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Patent number: 10097177Abstract: A switch device includes first and second switch units that are coupled respectively to first and second output terminals. Each of the first and second switch units includes a plurality of diodes and at least one semiconductor-controlled rectifier (SCR), where at least one of the diodes and one of the at least one SCR cooperatively permit a current to flow therethrough to a corresponding one of the first and second output terminals when each thereof operates in an ON state, and where at least one of the diodes and one of the at least one SCR cooperatively permit a current to flow therethrough from a corresponding one of the first and second output terminals when each thereof operates in an ON state.Type: GrantFiled: September 12, 2016Date of Patent: October 9, 2018Assignees: Lite-On Electronics (Guangzhou) Limited, Lite-On Technology Corp.Inventors: Wen-Che Tsai, Shih-Ming Chen, Yong-Long Lee, Jin-Yuan Lai
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Patent number: 10074558Abstract: The present disclosure provides a method that includes forming an isolation feature in a semiconductor substrate; forming a first fin and a second fin on the semiconductor substrate, wherein the first and second fins are laterally separated by the isolation feature; and forming an elongated contact feature landing on the first and second fins. The elongated contact feature is further embedded in the isolation feature, enclosing an air gap vertically between the contact feature and the isolation feature.Type: GrantFiled: November 1, 2017Date of Patent: September 11, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua-Feng Chen, Kuo-Hua Pan