Abstract: The disclosure is related to an RF signal processing apparatus. The apparatus includes a processor and a buffer memory circuit. The apparatus includes a host interface for connecting with a host and an RF circuit for transmitting and receiving RF signals. The processor processes the RF signals to or from the RF circuit. The processor converts the received RF signals into data, or converts the data into the RF signals to be transmitted. The buffer memory circuit has a controller and two buffer memories. This memory architecture allows a system to assign a task to a first buffer memory and another task to a second buffer memory without restricting that the conventional buffer memory is limited to doing one task at a time. This memory architecture can solve inefficiency problems due to insufficient data transmission since the conventional buffer memory cannot be filled within a limited time period.

Abstract: The disclosure is related to an RF signal processing apparatus. The apparatus includes a processor and a buffer memory circuit. The apparatus includes a host interface for connecting with a host and an RF circuit for transmitting and receiving RF signals. The processor processes the RF signals to or from the RF circuit. The processor converts the received RF signals into data, or converts the data into the RF signals to be transmitted. The buffer memory circuit has a controller and two buffer memories. This memory architecture allows a system to assign a task to a first buffer memory and another task to a second buffer memory without restricting that the conventional buffer memory is limited to doing one task at a time. This memory architecture can solve inefficiency problems due to insufficient data transmission since the conventional buffer memory cannot be filled within a limited time period.