Patents by Inventor Wen-Cheng Chang

Wen-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7100898
    Abstract: A lifting jack includes a lifting mechanism pivoted to a base and a support bracket member so as to lift or lower the support bracket member relative to the base, a driving shaft journalled on a right link pin to be rotated so as to move a left link pin relative to the right link pin, a reflecting member hinged to the base so as to enable the reflecting member to be displaced from a folded position to an unfolded position and to be disposed to reflect images of an object lifted by the support bracket member. Preferably, a lighting device is disposed to illuminate a desired area of the object. Two limit switches are disposed to prevent excess movement of the bracket support member.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: September 5, 2006
    Inventor: Wen-Cheng Chang
  • Publication number: 20040128318
    Abstract: A part number request processing system and method is provided which allows a part number requester to efficiently obtain the verification of the part quality. The system resides in a server having a part specification database for storing a plurality of part specification label having part information and corresponding supplier information and a part test database for storing a plurality of part test records having part information and corresponding part test information. When the server receives a request, it extracts the part number specification information and test results to verify if the parts requested meet the standard, if not met, the supplier is assessed; oppositely, if met the purchase request is sent to the supplier. After delivery of the parts, test information is entered into the server via a network system to update the part specification information and part test information to provide the verification of the part purchase request.
    Type: Application
    Filed: March 24, 2003
    Publication date: July 1, 2004
    Applicant: Inventec Corporation
    Inventors: Chin-Huan Peng, Li-Chuan Yu, Li-Ying Huang, Wen-Cheng Chang, Yo-Huang Chang, Chien-Yi Yang
  • Publication number: 20040073326
    Abstract: A method and a system for managing engineer-modified trial operation are provided, for use in an enterprise to perform automatic integration planning for engineer-modified related processes. By computer information management technology and network technology, an online trial operation procedure is executed for a confirmed engineer-modified project. This procedure involves material planning and uploading trial data to a quality control department after the trial is completed to produce a trial operation test report that is directed to associated departments. Compared to the prior art, the integration planning conducted by the proposed system allows employees of the enterprise to more easily access and manage data in real time, thereby improving operational efficiency of the enterprise.
    Type: Application
    Filed: March 7, 2003
    Publication date: April 15, 2004
    Inventors: Weng-Chang Chang, Wen-Cheng Chang, Chien-Ming Tseng, Chih-Chen Chen
  • Publication number: 20020114904
    Abstract: A ceramic sculpture for storing and releasing fragrance is provided which includes a bowl-like body of the ceramic sculpture with an indentation at the bottom with a vapor permeation barrier on the surface of the indentation; a unglazed ceramic base embedded into the indentation of the bowl-like body of the ceramic sculpture; and a fragrant substance placed in the indentation and the base, while fragrance is absorbed and released from the surface of the base. A method of making the ceramic sculpture for storing and releasing fragrance is also provided.
    Type: Application
    Filed: December 20, 2000
    Publication date: August 22, 2002
    Inventor: Wen-Cheng Chang
  • Patent number: 6352599
    Abstract: Magnetic nanocomposite materials including iron, rare earth elements, boron, refractory metals and cobalt which have favorable magnetic properties and are suitable for making bonded magnets are disclosed. Compositions of the present invention can be of the formula: (N1−yLay)vFe100−v−w−x−zCowMzBx, where M is at least one refractory metal selected from Ti, Zr, Hf, V, Nb, Ta, Cr, Mo and W; v is from about 5 to about 15; w is greater than or equal to 5; x is from about 9 to about 30; y is from about 0.05 to about 0.5; and z is from about 0.1 to about 5. Preferably M is at least Cr. These materials have good magnetic properties and are suitable for use in preparing bonded magnets.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: March 5, 2002
    Assignee: Santoku Corporation
    Inventors: Wen Cheng Chang, Bao-Min Ma, Qun Chen, Charles O. Bounds
  • Patent number: 6332933
    Abstract: Magnetic nanocomposite materials including iron, rare earth elements, boron, refractory metal and, optionally, cobalt are disclosed. Neodymium and lanthanum are preferred rare earth elements. The amounts of Nd, La, B and refractory metal are controlled in order to produce both hard and soft magnetic phases, as well as a refractory metal boride precipitated phase. The refractory metal boride precipitates serve as grain refiners and substantially improve the magnetic properties of the nanocomposite materials. The materials are particularly suitable for making bonded magnets.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: December 25, 2001
    Assignee: Santoku Corporation
    Inventors: Bao-Min Ma, Charles O. Bounds, Wen Cheng Chang, Qun Chen
  • Patent number: 6313516
    Abstract: A high-sheet-resistance polysilicon resistor for integrated circuits is achieved by using a two-layer polysilicon process. After forming FET gate electrodes and capacitor bottom electrodes from a polycide layer, a thin interpolysilicon oxide (IPO) layer is deposited to form the capacitor interelectrode dielectric. A doped polysilicon layer and an undoped polysilicon layer are deposited and patterned to form the resistor. The doped polysilicon layer is in-situ doped to minimize the temperature and voltage coefficients of resistivity. Since the undoped polysilicon layer has a very high resistance (infinite), the resistance is predominantly determined by the doped polysilicon layer.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: November 6, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Ming Tsui, Wen-Cheng Chang, Shung-Jen Yu
  • Patent number: 6147372
    Abstract: Device layouts are described which increase the photon current of a metal oxide semiconductor image sensor. The metal oxide semiconductor can be NMOS, PMOS, or CMOS. The key part of the photon current of the image sensors comes from the depletion region at the PN junction between the drain region and the substrate material. The layouts used significantly increase the area of this depletion region illuminated by a stream of photons. The layouts have a drain region which takes the shape of a number of parallel fingers perpendicular to the gate electrode, a number of parallel fingers parallel to the gate electrode, or a spiral. The drain regions of these layouts significantly increase the area of the drain depletion region illuminated by a stream of electrons.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: November 14, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hua-Yu Yang, Chih-Heng Shen, Wen-Cheng Chang
  • Patent number: 6054359
    Abstract: A high-sheet-resistance polysilicon resistor for integrated circuits is achieved by using a two-layer polysilicon process. After forming FET gate electrodes and capacitor bottom electrodes from a polycide layer, a thin interpolysilicon oxide (IPO) layer is deposited to form the capacitor interelectrode dielectric. A doped polysilicon layer and an undoped polysilicon layer are deposited and patterned to form the resistor. The doped polysilicon layer is in-situ doped to minimize the temperature and voltage coefficients of resistivity. Since the undoped polysilicon layer has a very high resistance (infinite), the resistance is predominantly determined by the doped polysilicon layer.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: April 25, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Ming Tsui, Wen-Cheng Chang, Shung-Jen Yu, Sheng-Yih Ting
  • Patent number: 5904570
    Abstract: The polymeric residues which remain after the plasma-enhanced subtractive etching of polycrystalline layers in reactive halogen-containing gases are removed by a combination ashing in oxygen gas and subsequent removal with an organic solvent.
    Type: Grant
    Filed: May 20, 1996
    Date of Patent: May 18, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Fu Chen, Bao-Ru Yang, Wen-Cheng Chang, Heng-Hsin Liu
  • Patent number: 5763316
    Abstract: A process for creating field oxide isolation for the micron and sub-micron devices in the high density integrated circuits has been developed. The junction leakage problem resulted from the trenches in the substrate formed after the removal of the silicon nitride mask, is avoided. The encroachment of the "bird's beak" into the small active device region is also minimized by this invention. These goals are accomplished by the addition of a polysilicon or amorphous silicon refill layer in the trenches after the removal of the silicon nitride oxidation mask in the isolation region, prior to field oxide oxidation process.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: June 9, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Fu Chen, Bao-Ru Yang, Wen-Cheng Chang
  • Patent number: 5719087
    Abstract: A protective cap of dielectric material is deposited by plasma-enhanced chemical vapor deposition on the surface of electrical bonding pads of semiconductor integrated circuits prior to deposition of the final passivation layer. The protective cap serves to isolate the pad surface from electrochemical or other interaction with the etching solution used to open contact holes through the passivation layer. This prevents the formation of surface damage and residues on the pad which lead to yield and reliability problem with integrated circuits.
    Type: Grant
    Filed: March 7, 1996
    Date of Patent: February 17, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen Fu Chen, Jie Shing Wu, Po-Tau Chu, Wen-Cheng Chang
  • Patent number: 5639342
    Abstract: A patterned silicon nitride layer formed over a semiconductor integrated circuit wafer having a layer of pad oxide is often used as a mask for subsequent processing steps. Etching of the silicon nitride layer is difficult to control and can create defects in the pad oxide layer which are difficult to detect before the manufacture of the semiconductor integrated circuit wafer is completed. A method is described using potassium hydroxide treatment and scanning electron microscope evaluation of a test wafer for detection of defects at the silicon nitride etching step. Continued processing of defective wafers can be terminated and the silicon nitride etching step can be controlled using this method.
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: June 17, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Sen Fu Chen, Wen Cheng Chang, Heng Hsin Liu, Bao Ru Yang