Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

Abstract: An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes.

Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a semiconductor die, a thermally conductive film, a substrate, a plurality of electrically conductive film patterns, and at least one insulator. The thermally conductive film is disposed on the bottom of the semiconductor die. The substrate is substantially comprised of the electrically conductive material or semiconductor material. Furthermore, a first hole is disposed on and passed all the way through the substrate, and the semiconductor die is disposed in the first hole. The electrically conductive film patterns are disposed on the substrate, and not contacting with each other. In addition, the insulator is connected between the semiconductor die and the substrate.

Abstract: An image sensor package and a method for fabricating thereof are provided. A substrate having an insulator filled cavity is provided with an image sensor device electrical connected to a metal layer, thereon. A covering plate is then disposed on the substrate. The substrate is subsequently thinned to expose the insulator. Removing a portion of the insulator, a hole is formed and a conductive layer is filled therein to form a via hole. Next, a solder ball is located over a backside of the substrate which is electrically connected to the metal layer through the via hole. The image sensor package is thinned, thus, the dimensions thereof are reduced.

Abstract: A submount and a manufacturing method thereof are provided. The submount, on which at least a semiconductor die is disposed, is mounted on a circuit board. The submount includes a substrate made of a conductive material or a semiconducting material, a plurality of conductive film patterns, and an insulating film pattern. A surface of the substrate includes a die-bonding area and a plurality of conductive areas. The conductive film patterns are individually distributed in the respective conductive areas. The insulating film pattern is disposed between the conductive film pattern and the insulating film pattern, but is not disposed in the die-bonding area. Furthermore, the semiconductor die is disposed in the die-bonding area and is electrically connected with the conductive film patterns. Because the insulating film pattern is not being disposed in the die-bonding area of the submount, the submount structure has improved heat transfer efficiency.

Abstract: The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad.

Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

Abstract: The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

Abstract: An embodiment of the present invention provides an electronic device package, which includes a chip having a first surface and an opposite second surface and a trench extending into a body of the chip along a direction from the second surface to the first surface, wherein a bottom portion of the trench includes at least two contact holes.

Abstract: Embodiments provide a semiconductor device package and a method for fabricating thereof. The package includes a silicon substrate having a semiconductor device and a metal layer thereon; an insulator ring formed in the silicon substrate and surrounding a portion of a silicon material below the metal layer; and a conductive layer disposed below a backside of the silicon substrate and extended to contact the portion of the silicon material surrounded by the insulator ring below the metal layer.

Abstract: A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.

Abstract: An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes.

Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

Abstract: The invention provides an image sensor package and a method for fabricating thereof. The package comprises a substrate having an image sensor device electrically connected to a metal layer thereon and a covering plate disposed over the substrate. A plurality of trench insulators is formed in the substrate, whereby the each trench insulator surrounds an isolation region each. A via hole is formed in the substrate within the isolation region and electrically connects to the metal layer to a solder ball thereby transmitting a signal from the image sensor device to an exterior circuit.

Abstract: An image sensor package and a method for fabricating thereof are provided. A substrate having an insulator filled cavity is provided with an image sensor device electrical connected to a metal layer, thereon. A covering plate is then disposed on the substrate. The substrate is subsequently thinned to expose the insulator. Removing a portion of the insulator, a hole is formed and a conductive layer is filled therein to form a via hole. Next, a solder ball is located over a backside of the substrate which is electrically connected to the metal layer through the via hole. The image sensor package is thinned, thus, the dimensions thereof are reduced.

Abstract: A new method is provided that extends the process of automation of the CMP process by monitoring the in-line removal rate, by using methods of curve-fitting that enable a reduction in the frequency of monitoring the removal rate of the CMP process, by enhancing the life expectancy of the polishing pad thereby further reducing the frequency of the required Preventive Maintenance and by allowing for the polishing of non-standard lots of wafers.

Abstract: A new method is provided that extends the process of automation of the CMP process by monitoring the in-line removal rate, by using methods of curve-fitting that enable a reduction in the frequency of monitoring the removal rate of the CMP process, by enhancing the life expectancy of the polishing pad thereby further reducing the frequency of the required Preventive Maintenance and by allowing for the polishing of non-standard lots of wafers.

Abstract: A new method is provided that extends the process of automation of the CMP process by monitoring the in-line removal rate, by using methods of curve-fitting that enable a reduction in the frequency of monitoring the removal rate of the CMP process, by enhancing the life expectancy of the polishing pad thereby further reducing the frequency of the required Preventive Maintenance and by allowing for the polishing of non-standard lots of wafers.